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SC1211 Datasheet(PDF) 8 Page - Semtech Corporation |
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SC1211 Datasheet(HTML) 8 Page - Semtech Corporation |
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8 / 11 page ![]() 8 © 2003 Semtech Corp. www.semtech.com POWER MANAGEMENT SC1211 Applications Information THEORY OF OPERATION The SC1211 is a high speed, Combi-SenseTM, dual out- put driver designed to drive top and bottom MOSFETs in a synchronous Buck converter. It features adaptive de- lay for shoot-through protection and VID-on-Fly opera- tion; internal LDO for optimum gate drive voltage; and Virtual Phase Node for Combi-SenseTM solution. These drivers combined with PWM controller SC2643VX form a multi-phase voltage regulator for advanced micropro- cessors. A three-phase voltage regulator with 12V input 60A output is shown in the Typical Application Circuit sec- tion. Startup and UVLO To startup the driver, a supply voltage is applied to VIN pin of the SC1211. The top and bottom gates are held low until VIN exceeds UVLO threshold of the driver, typi- cally 4.0V. Then the top gate remains low and the bot- tom gate is pulled high to turn on the bottom FET. Once VIN exceeds UVLO threshold of the PWM controller, typi- cally 7.5V, the soft-start begins and the PWM signal takes fully control of the gate transitions. Gate Transition and Shoot through Protection Refer to the Timing Diagrams section, the rising edge of the PWM input initiates the bottom FET turn-off and the top FET turn-on. After a short propagation delay (tPDL_BG), the bottom gate begins to fall (tF_BG). An adaptive circuit in the SC1211 monitors the bottom gate voltage to drop below 1.4V. Then after a preset delay time (tPDH_TG) is expired, the top gate turns on. The delay time is set to be 20ns typically. This prevents the top FET from turning on until the bottom FET is off. During the transition, the inductor current is freewheeling through the body diode of either bottom FET or top FET, upon the direction of the inductor current. The phase node could be low (ground) or high (VIN). The falling edge of the PWM input controls the top FET turn-off and the bottom FET turn-on. After a short propa- gation delay (tPDL_TG), the top gate begins to fall (tF_TG). As the inductor current is commutated from the top FET to the body diode of the bottom FET, the phase node begins to fall. The adaptive circuit in the SC1211 de- tects the phase node voltage. It holds the bottom FET off until the phase node voltage has dropped below 1.0V. This prevents the top and bottom FETs from conducting simultaneously or shoot-through. VID-on-Fly Operation Certain new processors have required to changing the VID dynamically during the operation, or refered as VID- on-Fly operation. A VID-on-Fly can occur under light load or heavy load conditions. At light load, it could force the converter to sink current. Upon turn-off of the top FET, the reversed inductor current has to be freewheeling through the body diode of the top FET instead of the bottom FET. As a result, the phase node voltage remains high. The SC1211 incorporates the ability by pulling the bottom gate to high internally, which over rides the adap- tive circuit and turns the bottom FET on. The delay time from the PWM falling egde to the bottom gate turn-on is set at 200ns typically. Virtual Phase Node for Combi-SenseTM Peak-Current-Mode control is widely employed in multi- phase voltage regulators. It features phase current bal- ance, fast transient response, and over current protec- tion, etc. These are essential to low-voltage high-cur- rent regulators designed for advanced microprocessors. Usually, a costly current sensing resistor is required to obtain the output inductor current information for the peak current control. The Combi-SenseTM technique fea- tured by the SC1211 is an approach to sense inductor current without using sensing resistor. The above circuit shows the concept of Combi-SenseTM technique. An internal totem pole (Qcst, Qcsb) gener- ates a VPN (Virtual Phase Node) signal. This VPN follows Inductor Current Signal Vout Qcst VIN Rcs C SC1211 PGND VIN VPN Lo Q2 Qcsb DRN Q1 + Co Ccs |
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