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DIX4192IPFBT Datasheet(PDF) 48 Page - Burr-Brown (TI) |
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DIX4192IPFBT Datasheet(HTML) 48 Page - Burr-Brown (TI) |
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48 / 60 page  www.ti.com DIX4192 SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 1B: General-Purpose Output 1 (GPO1) Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 GPO13 GPO12 GPO11 GPO10 GPO[13:10] General-Purpose Output 1 (GPO1) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO1. GPO13 GPO12 GPO11 GPO10 GPO1 Function 0 0 0 0 GPO1 is forced low (default) 0 0 0 1 GPO1 is forced high 0 0 1 0 Reserved 0 0 1 1 Transmitter interrupt, active low 0 1 0 0 Receiver interrupt, active low 0 1 0 1 Receiver 50/15 µs pre-emphasis, active low 0 1 1 0 Receiver non-audio data, active high 0 1 1 1 Receiver non-valid data, active high 1 0 0 0 Receiver channel status bit 1 0 0 1 Receiver user data bit 1 0 1 0 Receiver block start clock Receiver COPY bit 1 0 1 1 (0 = copyright asserted, 1 = copyright not asserted) Receiver L-bit 1 1 0 0 (0 = first generation or higher, 1 = original) 1 1 0 1 Receiver parity error, active high 1 1 1 0 Receiver internal sync clock 1 1 1 1 Transmitter internal sync clock Register 1C: General-Purpose Output 2 (GPO2) Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 GPO23 GPO22 GPO21 GPO20 GPO[23:20] General-Purpose Output 2 (GPO2) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO2. GPO23 GPO22 GPO21 GPO20 GPO2 Function 0 0 0 0 GPO2 is forced low (default) 0 0 0 1 GPO2 is forced high 0 0 1 0 Reserved 0 0 1 1 Transmitter interrupt, active low 0 1 0 0 Receiver interrupt, active low 0 1 0 1 Receiver 50/15 µs pre-emphasis, active low 0 1 1 0 Receiver non-audio data, active high 0 1 1 1 Receiver non-valid data, active high 1 0 0 0 Receiver channel status bit 1 0 0 1 Receiver user data bit 1 0 1 0 Receiver block start clock Receiver COPY bit 1 0 1 1 (0 = copyright asserted, 1 = copyright not asserted) Receiver L-bit 1 1 0 0 (0 = first generation or higher, 1 = original) 1 1 0 1 Receiver parity error, active high 1 1 1 0 Receiver internal sync clock 1 1 1 1 Transmitter internal sync clock 48 Submit Documentation Feedback |
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