DIX4192IPFBT datasheet(16/60 Pages) BURR-BROWN

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Precedingstate:

Preamble:

Channelcoding:

Description:

111 00

000 11

Channel

bframe

111 01

000 10

Channel

bframe

111 10

000 01

Channel1subframe andblockstart

Cl ck

(2xSourceBi

ate

)

SourceDataCoding

(NR )

AES3ChannelCoding

(BiphaseMark)

InsertPreamble

Code Below

Precedingstate,fr

ofthepreviousframe

omtheParitybit

PreambleZ(BlockStart)

PreambleCoding

DIGITAL INTERFACE TRANSMITTER (DIT) OPERATION

DIX4192

SBFS031C – JANUARY 2006 – REVISED JUNE 2006

PRODUCT OVERVIEW (continued)

The binary non-return to zero (NRZ) formatted audio and status source data for bits 4 through 31 of each

subframe are encoded utilizing a Biphase Mark format for transmission. This format allows for clock recovery at

the receiver end, as well as making the interface insensitive to the polarity of the balanced cable connections.

The preambles at the start of each subframe are encoded to intentionally violate the Biphase Mark formatting,

making their detection by the receiver reliable, as well as avoiding the possibility of audio and status data

imitating the preambles. Figure 9 shows the Biphase Mark and preamble encoding.

Although the AES3 standard originally defined transmission for sampling rates up to 48kHz, the interface is

capable of handling higher sampling rates, given that attention is paid to cable length and impedance matching.

Equalization at the receiver may also be required, depending on the cable and matching factors. It is also

possible to transmit and decode more than two channels of audio data utilizing the AES3 or related consumer

interfaces. Special encoding and/or compression algorithms are utilized to support multiple channels, including

the Dolby

® AC-3, DTS, MPEG-1/2, and other data reduced audio formats.

Figure 9. Biphase Mark Encoding

The DIT encodes a given two-channel or data-reduced audio input stream into an AES3-encoded output stream.

In addition to the encoding function, the DIT includes differential line driver and CMOS-buffered output functions.

The line driver is suitable for driving balanced or unbalanced line interfaces, while the CMOS-buffered output is

designed to drive external logic or line drivers, as well as optical transmitter modules. Figure 10 illustrates the

functional block diagram for the DIT.

The input of the DIT receives the audio data for Channels 1 and 2 from one of three possible sources: Port A,

Port B, or the DIR. By default, Port A is selected as the source. The DIT also requires a master clock source,

which may be provided by either the MCLK input (pin 25) or RXCKO (the DIR recovered master clock output). A

master clock divider is utilized to select the frame rate for the AES3-encoded output data. The TXDIV[1:0] bits in

control register 0x07 are utilized to select divide by 128, 256, 384, or 512 operation.

Channel status and user data for Channels 1 and 2 are input to the AES3 encoder via the corresponding

Transmitter Access (TA) data buffers. The TA data buffers are in turn loaded from the User Access (UA) buffers,

which are programmed via the SPI or I2C host interface, or loaded from the DIR Receiver Access (RA) data

buffers. The source of the channel status and user data is selected utilizing the TXCUS[1:0] bits in control

DIT is delayed by one block in relation to the audio data.

The validity (V) bit may be programmed using one of two sources. The VALSEL bit in control register 0x09 is

utilized to select the validity data source for the DIT block. The default source is the VALID bit in control register

0x07, which is written via the SPI or I2C host interface. The validity bit may also be transferred from the AES3

decoder output of the DIR, where the V bit for the DIT subframes tracks the decoded DIR value frame by frame.

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