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UPD78044F Datasheet(PDF) 50 Page - Renesas Technology Corp |
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UPD78044F Datasheet(HTML) 50 Page - Renesas Technology Corp |
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50 / 74 page  48 mPD78042F, 78043F, 78044F, 78045F (iii) SBI mode (SCK0: Internal clock output) Note R is a load resistance of the SCK0, SB0, or SB1 output line, and C is its load capacitance. (iv) SBI mode (SCK0: External clock input) Note R is a load resistance of the SB0 or SB1 output line, and C is its load capacitance. Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK0 cycle time tKCY3 VDD = 4.5 to 5.5 V 800 ns 3200 ns SCK0 high, low-level width tKH3 VDD = 4.5 to 5.5 V tKCY3/2 – 50 ns tKL3 tKCY3/2 – 150 ns SB0, SB1 setup time to SCK0 ↑ tSIK3 VDD = 4.5 to 5.5 V 100 ns 300 ns SB0, SB1 hold time from tKSI3 tKCY3/2 ns SCK0 ↑ SCK0 ØÆSB0, SB1 output tKSO3 R = 1 k W, VDD = 4.5 to 5.5 V 0 250 ns delay time C = 100 pFNote 0 1000 ns SCK0 ↑ÆSB0, SB1Ø tKSB tKCY3 ns SB0, SB1 ØÆ SCK0Ø tSBK tKCY3 ns SB0, SB1 high-level width tSBH tKCY3 ns SB0, SB1 low-level width tSBL tKCY3 ns Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK0 cycle time tKCY4 VDD = 4.5 to 5.5 V 800 ns 3200 ns SCK0 high, low-level width tKH4 VDD = 4.5 to 5.5 V 400 ns tKL4 1600 ns SB0, SB1 setup time to SCK0 ↑ tSIK4 VDD = 4.5 to 5.5 V 100 ns 300 ns SB0, SB1 hold time from tKSI4 tKCY4/2 ns SCK0 ↑ SCK0 ØÆSB0, SB1 output tKSO4 R = 1 k W, VDD = 4.5 to 5.5 V 0 300 ns delay time C = 100 pFNote 0 1000 ns SCK0 ↑ÆSB0, SB1Ø tKSB tKCY4 ns SB0, SB1 ØÆSCK0Ø tSBK tKCY4 ns SB0, SB1 high-level witdh tSBH tKCY4 ns SB0, SB1 low-level width tSBL tKCY4 ns SCK0 rise time and fall time tR4 160 ns tF4 |
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