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UPD78323LP Datasheet(PDF) 71 Page - Renesas Technology Corp

Part # UPD78323LP
Description  MOS INTEGRATED CIRCUIT
PDF  88 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD78323LP Datasheet(HTML) 71 Page - Renesas Technology Corp

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69
µPD78323, 78324
SERIAL OPERATION (TA = –10 to +70
°C, VDD = +5 V ±10 %, VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
SCK output
Internal division by 8
1
µs
SCK input
External clock
1
µs
SCK output
Internal division by 8
420
ns
SCK input
External clock
420
ns
SCK output
Internal division by 8
420
ns
SCK input
External clock
420
ns
SI setup time (to SCK
↑)tSRXSK
80
ns
SI hold time (from SCK
↑)tHSKRX
80
ns
SO delay time from SCK
↓
tDSKTX
R = 1 k
Ω, C = 100 pF
210
ns
Serial clock cycle time
Serial clock low-level width
Serial clock high-level width
tCYSK
tWSKL
tWSKH
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
NMI high/low-level width
tWNIH,tWNIL
5
µs
INTP0 high/low-level width
tWI0H,tWI0L
8T
tCYK
INTP1 high/low-level width
tWI1H,tWI1L
8T
tCYK
INTP2 high/low-evel width
tWI2H,tWI2L
8T
tCYK
NTP3 high/low-level width
tWI3H,tWI3L
8T
tCYK
NTP4 high/low-level width
tWI4H,tWI4L
8T
tCYK
INTP5 high/low-level width
tWI5H,tWI5L
8T
tCYK
INTP6 high/low-level width
tWI6H,tWI6L
8T
tCYK
RESET high/low-level width
tWRSH,tWRSL
5
µs
TI high/low-level width
tWTIH,tWTIL
In TM1 event counter mode
8T
tCYK
OTHER OPERATION (TA = –10 to +70
°C, VDD = +5 V ±10 %, VSS = 0 V)



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