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10/19

Rev.0.0

Dual-ChannelIsolatedGateDriver

BTD21520x

8.5CMTITesting

Figure5.SimplifiedCMTITestSetup

8.6UVLODelayDuringICPower-On

At the process of device power-on, there is a time delay from the start of the supply voltage rise to the UVLO recovery

threshold, and then to the device output response, as shown in the figures below.tVCC+ to OUT is primary side power-on

UVLO delay (typical value 40us), and tVDD + to OUT is secondary side power-on UVLO delay (typical value 50us).It is suggest-

ed that after powering on the driver IC, adequate time margin is reserved before sending PWM signal to IC.If IN1 or IN2

is already at high level before VCC or VDDx reaches the recovery threshold, after tVCC+ to OUT or tVDD+ to OUT counting from the

time point when VCC or VDDx reaches the recovery threshold, the corresponding output will jump to a high level.How-

ever, when the VCC or VDDx voltage drops to the UVLO lockout threshold, the output will be completely blocked within

1us.This asymmetric design is to ensure safe operation of a VCC or VDDx in the event of a power failure.

Figure6-1.UVLOdelaywhentheVCCispoweredon

Figure6-2.UVLOdelaywhentheVDDxispoweredon

Functional

Isolation

VCC

VDD

VCC

Common Mode

Surge Generator

IN1

1

2

IN2

GND

DIS

DT

VCC

3

VCC

5

8

4

6

VDD1

OUT1

VDD2

OUT2

VEE2

VEE1

11

9

VEE

10

16

15

14

OUT1

OUT2

VCC,INx

OUT

VDD

tVCC+ to OUT

VVCC-ON

VVCC-OFF

VCC,INx

OUTx

VDDx

tVDD+ to OUT

VVDD-ON

VVDD-OFF