STE10A datasheet(54/82 Pages) STMICROELECTRONICS

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Registers and descriptors description

STE10/100A

54/82

Power management. Enables the STE10/100A

power management abilities. When this bit is set

into “0” the STE10/100A will set the Cap_Ptr

power management capabilities. The value of

this bit will be mapped to NC (CR1 bit 20). In PCI

power management mode, the wake up frames

include “Magic Packet”, “Unicast”, and

“Muliticast”.

from EEPROM

WOL

Wake on LAN mode enable. When this bit is set

to ‘1’, then the STE10/100A enters wake on LAN

mode and enters the sleep state.

Once the STE10/100A enters the sleep state, it

remains there until: the wake up event occurs,

the WOL bit is cleared, or a reset (software or

hardware) happens.

In wake on LAN mode the wake-up frame is

“Magic Packet” only.

from EEPROM

R/W

17~7

---

Reserved

RWP

Reset wake-up pattern data register pointer

R/W

5PAUSE

Disable or enable the PAUSE function for flow

control. The default value of PAUSE is

determined by the result of auto-negotiation. The

driver software can overwrite this bit to enable or

disable it after the auto-negotiation has

completed.

0: PAUSE function is disabled.

1: PAUSE function is enabled

Depends on

the result of

auto-

negotiation

R/W

4RTE

Receive threshold enable.

1: the receive FIFO threshold is enabled.

0: disable the receive FIFO threshold selection in

DRT (bits 3~2), and the receive threshold is set

to the default 64 bytes.

0R/W

3~2

DRT

Drain receive threshold

00: 32 bytes (8 DW)

01: 64 bytes (16 DW)

10: store-and -forward

11: reserved

R/W

SINT

Software interrupt.

R/W

0ATUR

1: enable automatically transmit-underrun

recovery.

0R/W

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

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