STE10A datasheet(55/82 Pages) STMICROELECTRONICS

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STE10/100A

Registers and descriptors description

55/82

CSR19 (offset = 8ch), PCIC - PCI bus performance counter

31~16

CLKCNT

The number of PCI clocks from read request

asserted to access completed. This PCI clock

count is accumulated for all the read command

cycles from the last CSR19 read to the current

CSR19 read.

0RO*

15~8

---

Reserved

7~0

DWCNT

The number of double words accessed by the

last bus master. This double word count is

accumulated for all bus master data transactions

from the last CSR19 read to the current CSR19

read.

0RO*

RO* = Read only and cleared by reading.

CSR20 (offset = 90h), PMCSR - Power management command and status

(The same register value mapping to CR49-PMR1)

31~16

---

Reserved

PMES

PME_Status. This bit is set whenever the

STE10/100A detects a wake-up event,

regardless of the state of the PME-En bit.

Writing a “1” to this bit will clear it, causing the

STE10/100A to deassert PME# (if so enabled).

Writing a “0” has no effect.

0RO

14,13

DSCAL

Data_Scale. Indicates the scaling factor to be

used when interpreting the value of the data

that implements the data register.

The STE10/100A does not support data register

and Data_Scale.

00b

12~9

DSEL

Data_Select. This four bit field is used to select

which data is to be reported through the data

required for any function that implements the

data register.

The STE10/100A does not support Data_select.

0000b

8PME_En

PME_En. When set, enables the STE10/100A to

assert PME#. When cleared, disables the PME#

assertion.

0RO

7~2

---

Reserved

000000b

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

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