MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED

MPQ4480 Rev. 1.0

www.MonolithicPower.com

4

7/2/2019

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2019 MPS. All Rights Reserved.

PIN FUNCTIONS

Pin #

Name

Description

1, 5, 13, 17

PGND

Power ground. Reference ground of the regulated output voltage. PGND requires

extra care during PCB layout. Connect to GND with copper traces and vias. All

PGND pins must be connected together.

2, 16

RGND

Remote power ground. There is an internal 4mΩ current-sensing resistor from

RGND to PGND (pin 17 and pin 1).

3,15

IN

Supply voltage. The MPQ4480 operates from a 4.2V to 36V input voltage. CIN

prevents large voltage spikes at the input. Place CIN as close to the IC as possible.

IN is the drain of the internal power device, and provides the power supply for the

entire chip.

4, 8, 9, 14

SW

Switch output. These pins must be connected together by a PCB trace. Use a wide

PCB trace to make the connection.

6

AGND

Analog ground. Connect AGND to PGND.

7

VCC

Internal 5.05V LDO regulator output. Decouple with a 1µF capacitor.

10

BST

Bootstrap. A 0.22µF capacitor is connected between SW and BST to form a

floating supply across the high-side switch driver.

11

EN

On/off control input. The enable pin is an internal auto pull-up with a 7

µA current

source. EN has two stage thresholds: when EN is higher than ~1V, the VCC and

bias circuitry will be enabled; when EN is higher than 2V, the buck switcher starts to

work.

12

FREQ/SYNC

Switching frequency program input. Connect a resistor from FREQ to GND to set

the switching frequency. This pin also serves as a frequency-synchronous clock

input.

18, 19, 20,

21

NC

No connection. These pins should be left floating.

22

VDROP

Line drop amplitude selection. Three levels can be programmable by pulling

VDROP to GND or VCC, or floating.

23

ILIM

Output CC current limit set pin. Pull ILIM to VCC, GND, or float to set three

different current limit levels.

24

GATE

Gate drive for external, low-side, N-channel power MOSFET. Open-drain

structure. The GATE pin is pulled low to turn off the power MOSFET when the

secondary current RGND-to-PGND limit is triggered.

25

FB

Feedback. Connect to the tap of an external resistor divider from the output to GND

to set the output voltage.