ES9028Q2M datasheet(17/45 Pages) ESS

17 / 45 page

January 16, 2020

0.41

ES9028Q2M Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643-

8800 • WWW.ESSTECH.COM

8 bit, Read-Write Register, Default = 0x2

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

master_clock_enable

clock_divider_select

sync_mode

stop_div

Default

Bit

Mnemonic

Description

[7]

master_clock_enable

1’b0 disables master mode (default)

1’b1 enables master mode (driving Bit clock and Frame Clock)

[6:5]

clock_divider_select

’b00: Bit Clock frequency = MCLK / 4 (default)

’b01: Bit Clock frequency = MCLK / 8

’b10: Bit Clock frequency = MCLK / 16

’b11: Bit Clock frequency = MCLK / 16

Frame Clock frequency = Bit Clock frequency / 64

[4]

sync_mode

1’b0 for normal operation of the DPLL and ASRC.

’b1 to enable quick lock if the fs & MCLK are synchronous & MCLK is 128 x FSR.

Note: quick lock can only be used in PCM normal mode

[3:0]

stop_div

Sets the number of FSR edges that must occur before the DPLL and

ASRC can lock on to the incoming signal.

’d0 = 16384 FSR edges

’d1 = 8192 FSR edges

’d2 = 5461 FSR edges (default)

’d3 = 4096 FSR edges

’d4 = 3276 FSR edges

’d5 = 2730 FSR edges

’d6 = 2340 FSR edges

’d7 = 2048 FSR edges

’d8 = 1820 FSR edges

’d9 = 1638 FSR edges

’d10 = 1489 FSR edges

’d11 = 1365 FSR edges

’d12 = 1260 FSR edges

’d13 = 1170 FSR edges

’d14 = 1092 FSR edges

’d15 = 1024 FSR edges

For correct operation, master mode

should only be enabled when the DAC’s input mode is set to I2S, and when i2s_length is

set to 32-bit and i2s_mode is set to I2S in register 1.

When master mode is enabled, the DATA_CLK pin will output Bit Clock and the DATA1 pin will output Frame Clock at

frequencies specified by clock divider select.

When PCM data with FSR > 96kHz

is used, stop_div should be set to 4’d0 (16384 FSR edges).

ES9028Q2M Datasheet(PDF) 17 Page - ESS Technology,Inc

ES9028Q2M Datasheet(HTML) 17 Page - ESS Technology,Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL