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ES9028Q2M Datasheet(PDF) 11 Page - ESS Technology,Inc

Part # ES9028Q2M
Description  32-Bit Stereo Low Power Audio DAC
PDF  45 Pages
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9028Q2M Datasheet(HTML) 11 Page - ESS Technology,Inc

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January 16, 2020
0.41
ES9028Q2M Datasheet
11
ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643-
8800 • WWW.ESSTECH.COM
Audio Interface Formats
Several interface formats are provided so that direct connection to common audio processors is possible. The available
formats are shown in the following diagrams. The audio interface format can be set by programming the registers.
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB MSB
31 30
BCLK
LRCLK
LEFT
RIGHT
LEFT JUSTIFIED FORMAT
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB MSB
31 30
BCLK
LRCLK
LEFT
RIGHT
I2S FORMAT
23 22 21
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
24-bit
MSB
LSB MSB
LSB MSB
23 22
15 14 13
2
1
0
15 14 13
2
1
0
15 14 13
2
1
0
15 14 13
2
1
0
SIN
16-bit
MSB
LSB MSB
LSB MSB
15 14
23 22 21
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
24-bit
MSB
LSB MSB
LSB MSB
23 22
15 14 13
2
1
0
15 14 13
2
1
0
15 14 13
2
1
0
15 14 13
2
1
0
SIN
16-bit
MSB
LSB MSB
LSB MSB
15 14
Note: for Left-Justified and I2S formats, the following number of BCLKs is present per (left plus right) frame:
•
16-bit mode: 32 BCLKs
•
24-bit mode: 48 BCLKs
•
32-bit mode: 64 BCLKs
DCLK
DSD1, DSD2
DCLK
DSD1, DSD2
31 30 29
2
1
0
31 30 29
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB
MSB
MSB
LSB
LSB
19 18 17
2
1
0
19 18 17
2
1
0
MSB
MSB
LSB
LSB
15 14 13
2
1
0
15 14 13
2
1
0
MSB
MSB
LSB
LSB
23 22
MSB
MSB
19 18
MSB
15 14
MSB
31 30
SIN
24-bit
SIN
20bit
SIN
16bit
BCLK
LRCLK
LEFT
RIGHT
FIGURE 1A
FIGURE 1A
FIGURE 1A
FIGURE 1A
LEFT JUSTIFIED FORMAT
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB
MSB
MSB
LSB
LSB
19 18 17
2
1
0
19 18 17
2
1
0
MSB
MSB
LSB
LSB
15 14 13
2
1
0
15 14 13
2
1
0
MSB
MSB
LSB
LSB
23 22
MSB
MSB
19 18
MSB
15 14
MSB
31 30
SIN
24-bit
SIN
20bit
SIN
16bit
BCLK
LRCLK
LEFT
RIGHT
FIGURE 1A
FIGURE 1A
FIGURE 1A
FIGURE 1A
LEFT JUSTIFIED FORMAT
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB
MSB
MSB
LSB
LSB
19 18 17
2
1
0
19 18 17
2
1
0
MSB
MSB
LSB
LSB
15 14 13
2
1
0
15 14 13
2
1
0
MSB
MSB
LSB
LSB
MSB
31 30
SIN
24-bit
SIN
20bit
SIN
16bit
BCLK
LRCLK
LEFT
RIGHT
FIGURE 2A
FIGURE 2A
FIGURE 2A
FIGURE 2A
RIGHT JUSTIFIED FORMAT
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB
MSB
MSB
LSB
LSB
19 18 17
2
1
0
19 18 17
2
1
0
MSB
MSB
LSB
LSB
15 14 13
2
1
0
15 14 13
2
1
0
MSB
MSB
LSB
LSB
23 22
MSB
MSB
19 18
MSB
15 14
MSB
31 30
SIN
24-bit
SIN
20bit
SIN
16bit
BCLK
LRCLK
LEFT
RIGHT
FIGURE 3A
FIGURE 3A
FIGURE 3A
FIGURE 3A
I2S FORMAT
D..
D0
D1
D2
D3
D4
D1
D2
DCLK
FIGURE 4A
D..
D0
D1
D2
D3
D4
D1
D2
DCLK
FIGURE 4B
D..
D0
D1
D2
D3
D4
DSD NORMAL MODE
DSD PHASE MODE



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