ES9028Q2M datasheet(27/45 Pages) ESS

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January 16, 2020

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ES9028Q2M Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643-

8800 • WWW.ESSTECH.COM

8-bit, Read-Write Register, Default = 0x00

Bits

[7:4]

[3]

[2]

[1]

[0]

Mnemonic

reserved *

sb_aux_wk_en

sb_aux_wk_override

sb_drv_strength_en

sb_drv_strength_override

Default

Bit

Mnemonic

Description

[7:4]

reserved *

[3]

sb_aux_wk_en

1’b1 = enables the aux weak enable (only when override is set to 1’b1)

1’b0 = disables the aux weak enable (default)

[2]

sb_aux_wk_override

1’b1 = enables the override on SLIMbus aux weak

1’b0 = disables the override on SLIMbus aux weak (default)

[1]

sb_drv_strength_en

1’b1 = sets the SLIMbus drive strength enable (only when override is set to 1’b1)

1’b0 = disables the SLIMbus drive strength enable (default)

[0]

sb_drv_strength_override

1’b1 = enables the override on SLIMbus drive strength

1’b0 = disables the override on SLIMbus drive strength (default)

* All Reserved Bits in Register #43 must be set to the indicated logic level to ensure correct device operation.

8 bit, Read-Only Register

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

reserved

revision

chip_id

automute_status

lock_status

Bit

Mnemonic

Description

[7:6]

reserved

[5]

revision

’

[4:2]

chip_id

3’d1 => ES9028Q2M

[1]

automute_status

’b0 => Automute condition is inactive.

1’b1 => Automute condition is active.

[0]

lock_status

’b0 => The Jitter Eliminator is not locked to an incoming signal.

1’b1 => The Jitter Eliminator is locked to an incoming signal.

8 bit, Read-Only Register

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

reserved

gpio_I[1:0]

Bit

Mnemonic

Description

[7:2]

reserved

[1]

gpio_I[1]

Status of pin GPIO2

[0]

gpio_I[0]

Status of pin GPIO1

ES9028Q2M Datasheet(PDF) 27 Page - ESS Technology,Inc

ES9028Q2M Datasheet(HTML) 27 Page - ESS Technology,Inc

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