ADFS7124-8BBCPZ datasheet(50/93 Pages) AD

50 / 93 page

Data Sheet

ADFS7124-8

ADC CIRCUIT INFORMATION

analog.com

Rev. 0 | 50 of 93

In the power-down mode, all blocks are powered down, including

the LDOs. All registers lose their contents, and the digital outputs

P1 to P4 are placed in tristate. To prevent accidental entry to the

power-down mode, the ADC must first be placed into the standby

mode. If an external controller clock is being used, keep it active

until the device is placed in the power-down mode. Exiting the

power-down mode requires 64 SCLK cycles with CS = 0 and DIN =

1, that is, a serial interface reset. The ADFS7124-8 requires 2 ms

typically to power up and settle. After this time, the user can access

the on-chip registers. The power-down current is 2 µA typically.

DIGITAL INTERFACE

The programmable functions of the ADFS7124-8 are controlled

using a set of on-chip registers. Data is written to these registers

through the serial interface. Read access to the on-chip registers is

also provided by this interface. All communications with the device

must start with a write to the communications register. After power-

on or reset, the device expects a write to its communications regis-

ter. The data written to this register determines whether the next

operation is a read operation or a write operation, and determines

to which register this read or write operation occurs. Therefore,

write access to any of the other registers on the devices begins with

a write operation to the communications register, followed by a write

to the selected register. A read operation from any other register

(except when continuous read mode is selected) starts with a write

to the communications register, followed by a read operation from

the selected register.

The serial interface of the ADFS7124-8 consists of four signals:

CS, DIN, SCLK, and DOUT/RDY. The DIN line transfers data into

the on-chip registers, whereas DOUT/RDY accesses data from the

on-chip registers. SCLK is the serial clock input for the device, and

all data transfers (either on DIN or DOUT/RDY) occur with respect

to the SCLK signal. The DOUT/RDY pin also operates as a data

ready signal; the line goes low when a new data-word is available in

the output register. It is reset high when a read operation from the

data register is complete. It also goes high before the data register

updates to indicate when not to read from the device, to ensure that

a data read is not attempted while the register is being updated.

CS is used to select a device. It can decode the ADFS7124-8 in

systems where several components are connected to the serial

bus.

Figure 3 and Figure 4 show timing diagrams for interfacing to the

ADFS7124-8 with CS decoding the devices. Figure 3 shows the

timing for a read operation from the output shift register of the

ADFS7124-8. Figure 4 shows the timing for a write operation to the

input shift register. A delay is required between consecutive SPI

communications. Figure 5 shows the delay required between SPI

read/write operations. It is possible to read the same word from

the data register several times, even though the DOUT/RDY line

returns high after the first read operation. However, care must be

taken to ensure that the read operations are complete before the

next output update occurs. In the continuous read mode, the data

The serial interface can operate in the 3-wire mode by tying CS low.

In this case, the SCLK, DIN, and DOUT/RDY lines communicate

with the ADFS7124-8. The end of the conversion can be monitored

using the RDY bit in the status register. This scheme is suitable

for interfacing to microcontrollers. If CS is required as a decoding

signal, it can be generated from a port pin. For microcontroller

interfaces, it is recommended that SCLK is idle high between data

transfers.

The ADFS7124-8 can be operated with CS being used as a frame

synchronization signal. This scheme is useful for digital signal

processing (DSP) interfaces. In this case, the first bit (MSB) is

effectively clocked out by CS, because CS normally occurs after the

falling edge of SCLK in DSPs. SCLK can continue to run between

data transfers, provided the timing numbers are obeyed.

CS must be used to frame read and write operations and

the CS_EN bit in the ADC_CONTROL register must be set

when the diagnostics SPI_READ_ERR, SPI_WRITE_ERR, or

SPI_SCLK_CNT_ERR are enabled.

The serial interface can be reset by writing a series of 1s on the

DIN input. See the Reset section for more details. Reset returns

the interface to the state in which it is expecting a write to the

communications register

The ADFS7124-8 can be configured to continuously convert or

perform a single conversion (see Figure 78 through Figure 80).

Single Conversion Mode

In the single conversion mode, the ADFS7124-8 performs a single

conversion and is placed in the standby mode after the conversion

is complete. If a controller clock is present (external controller clock

or the internal oscillator is enabled), DOUT/RDY goes low to indi-

cate the completion of a conversion. When the data-word is read

from the data register, DOUT/RDY goes high. The data register can

be read several times, if required, even when DOUT/RDY is high.

Do not read the ADC_CONTROL register close to the completion of

a conversion because the mode bits are being updated by the ADC

to indicate that the ADC is in the standby mode.

If several channels are enabled, the ADC automatically sequences

through the enabled channels and performs a conversion on each

channel. When a conversion is started, DOUT/RDY goes high and

remains high until a valid conversion is available and CS is low.

As soon as the conversion is available, DOUT/RDY goes low.

The ADC then selects the next channel and begins a conversion.

Read the present conversion while the next conversion is being

performed. As soon as the next conversion is complete, the data

to read the conversion. When the ADC has performed a single

conversion on each of the selected channels, it returns to the

standby mode.

If the DATA_STATUS bit in the ADC_CONTROL register is set

to 1, the contents of the status register are output along with

ADFS7124-8BBCPZ Datasheet(PDF) 50 Page - Analog Devices

ADFS7124-8BBCPZ Datasheet(HTML) 50 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

Datasheet Download

Link URL