ADFS7124-8BBCPZ datasheet(54/93 Pages) AD

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Data Sheet

ADFS7124-8

ADC CIRCUIT INFORMATION

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Rev. 0 | 54 of 93

is used in the unipolar mode with a required span of VREF/gain, the

offset range that the system calibration can handle is from −1.05

× VREF/gain to +0.05 × VREF/gain. Similarly, if the device is used

in the unipolar mode and required to remove an offset of 0.2 ×

VREF/gain, the span range that the system calibration can handle is

0.85 × VREF/gain.

If the device is used in the bipolar mode with a required span of

±0.4 × VREF/gain, then the offset range that the system calibration

can handle is from −0.65 × VREF/gain to +0.65 × VREF/gain. If

the device is used in the bipolar mode with a required span of

±VREF/gain, the offset range the system calibration can handle is

from −0.05 × VREF/gain to +0.05 × VREF/gain. Similarly, if the device

is used in the bipolar mode and required to remove an offset of ±0.2

× VREF/gain, the span range that the system calibration can handle

is ±0.85 × VREF/gain.

SYSTEM SYNCHRONIZATION

The SYNC input allows the user to reset the modulator and digital

filter without affecting any of the setup conditions on the device.

This allows the user to start gathering samples of the analog input

from a known point in time, that is, the rising edge of SYNC. Take

SYNC low for at least four controller clock cycles to implement the

synchronization function.

If multiple ADFS7124-8 devices are operated from a common con-

troller clock, they can be synchronized so that their data registers

are updated simultaneously. A falling edge on the SYNC pin resets

the digital filter and analog modulator, and places the ADFS7124-8

into a consistent, known state. While the SYNC pin is low, the

ADFS7124-8 is maintained in this state. On the SYNC rising edge,

the modulator and filter exit this reset state and, on the next clock

edge, the device starts to gather input samples again. In a system

using multiple ADFS7124-8 devices, a common signal to their

SYNC pins synchronizes their operation. This is normally performed

after each ADFS7124-8 has performed its own calibration or has

calibration coefficients loaded into its calibration registers. The

conversions from the ADFS7124-8 devices are then synchronized.

The device exits reset on the controller clock falling edge following

the SYNC low to high transition. Therefore, when multiple devices

are being synchronized, pull the SYNC pin high on the controller

clock rising edge to ensure that all devices begin sampling on

the controller clock falling edge. If the SYNC pin is not taken

high in sufficient time, it is possible to have a difference of one

controller clock cycle between the devices; that is, the instant at

which conversions are available differs from device to device by a

maximum of one controller clock cycle.

The SYNC pin can also be used as a start conversion command.

In this mode, the rising edge of SYNC starts conversion and the

falling edge of RDY indicates when the conversion is complete. The

settling time of the filter must be allowed for each data register

update. For example, if the ADC is configured to use the sinc4

filter and zero latency is disabled, the settling time equals 4/fADC,

where fADC is the output data rate when continuously converting on

a single channel.

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