TLK2218ZPV datasheet(35/39 Pages) TI

Part #	TLK2218ZPV

Description	8-PORT GIGABIT ETHERNET TRANSCEIVER

PDF	39 Pages

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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LVCMOS INPUT TIMING REQUIREMENTS

TLK2218

SLLS734 – FEBRUARY 2007

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS(1)

MIN

TYP(1)

MAX

UNIT

tsu

TDxx[9:0] setup prior to TCLKx transition high or low

Timing relative to 0.5 VDDQ,

1.4

See Figure 15

TDxx[9:0] hold after TCLKx transition high or low

Timing relative to 0.5 VDD,

0.0

See Figure 15

t(Pulse)(2)

‡ TCLKx clock period divided by 2

Timing relative to 0.5 VDDQ,

3.85

See Figure 16

(1)

Timings valid for VIH no less than 80% of VDDQ and VIL no higher than 20% VDDQ.

(2)

TCLKB is assumed to be frequency locked to REFCLK with only phase differences.

Figure 15. LVCMOS Source Centered Data Input Timing Requirements

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TLK2218ZPV Datasheet(PDF) 35 Page - Texas Instruments