AS7030B datasheet(104/129 Pages) AMSCO

104 / 129 page

Document Feedback

AS7030B

Functional Description

Datasheet

• PUBLIC

DS000716

• v1-00 • 2020-Jun-10

128

│ 103

Addr: 0x8a

ADC_CFGC

Bit

Bit Name

Default

Access

Bit Description

adc_selfpd

1: Power down the ADC when not converting; use

this to conserve power, but set adc_settling_time

to minimum 64

μs to permit settling of the ADC

reference buffer.

0: Always enable ADC

adc_discharge

0: Suppress ADC capacitor discharging

– use with

caution

1: Discharge ADC capacitor before tracking

If asserted, the capacitor is discharged before the

tracking phase. If zero, the discharge phase is

suppressed and the tracking phase is started one

cycle earlier

2:0

adc_settling_time

ADC settling time: Use with synchronous

demodulator. It defines the number of ADC clock

cycles the sampling window is kept open

additionally.

If the gain stage in the optical frontend is used

(gain_byp=0), set this to minimum 8 µs. If

adc_selfpd=1, set this to minimum 64 µs.

Setting

Periods

µs

(@500 kHz)

µs

(@250 kHz)

128

256

128

256

512

256

512

1 ms

ADC_CHANNEL_MASK_L (Address 0x8b)

Figure 135:

ADC_CHANNEL_MASK_L Register

Addr: 0x8b

ADC_CHANNEL_MASK_L

Bit

Bit Name

Default

Access

Bit Description

adc_channel_mask_pregain

Pregain channel selection

adc_channel_mask_afe

Electrical front end

AS7030B Datasheet(PDF) 104 Page - ams AG

AS7030B Datasheet(HTML) 104 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL