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AS7030B Datasheet(PDF) 122 Page - ams AG |
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AS7030B Datasheet(HTML) 122 Page - ams AG |
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122 / 129 page ![]() Document Feedback AS7030B Functional Description Datasheet • PUBLIC DS000716 • v1-00 • 2020-Jun-10 128 │ 121 INTENAB (Address 0xa8) Figure 167: INTENAB Register Addr: 0xa8 INTENAB Bit Bit Name Default Access Bit Description 7 irq_led_supply_low_enab 0 RW 1: Enable LED supply low interrupt 6 irq_clipdetect_enab 0 RW 1: Enable clipdetect interrupt 5 irq_fifooverflow_ena 0 RW 1: Enable fifooverflow interrupt 4 irq_fifothreshold_enab 0 RW 1: Enable fifothreshold interrupt 3 irq_adc_threshold_enab 0 RW 1: Enable irq_adc_threshold as an interrupt source 2 irq_ltf_enab 0 RW 1: Enable LTF as an interrupt source 1 irq_sequencer_enab 0 RW 1: Enable irq_sequencer as an interrupt source 0 irq_adc_enab 0 RW 1: Enable irq_adc as an interrupt source Each of the STATUS register bits can cause an interrupt (register INTR) if the respective bit is asserted in the INTENAB register INTENAB2 (Address 0xa9) Figure 168: INTENAB2 Register Addr: 0xa9 INTENAB2 Bit Bit Name Default Access Bit Description 7:3 Not used 0 RW Not used 2 irq_ltf1_threshold_enab 0 RW 1: Enable ltf_treshold_high or ltf_treshold_low in ltf1 as interrupt source 1 irq_ltf0_threshold_enab 0 RW 1: Enable ltf_treshold_high or ltf_treshold_low in ltf0 as interrupt source 0 irq_ecg_threshold_enab 0 RW 1: Enable ecg_treshold_high or ecg_treshold_low as interrupt source |
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