WM8581 datasheet(53/100 Pages) WOLFSON

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Production Data

WM8581

PD Rev 4.0 April 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PLLA 4

03h

PRESCALE_A

PLLB 4

07h

PRESCALE_B

PLL Pre-scale Divider Select

0 = Divide by 1 (PLL input clock =

oscillator clock)

1 = Divide by 2 (PLL input clock =

oscillator clock

÷ 2)

Note: PRESCALE_A must be

set to the same value as

PRESCALE_B in PLL S/PDIF

receiver mode.

PLLA 4

03h

4:3

FREQMODE_A

[1:0]

PLLB 4

07h

4:3

FREQMODE_B

[1:0]

PLL Output Divider Select

PLL S/PDIF Receiver Mode

FREQMODE_A is automatically

controlled. FREQMODE_B is not

used.

PLL User Mode

Used in conjunction with the

POSTSCALE_x bits. Refer to Table

44.

PLLA 4

03h

POSTSCALE_A

PLLB 4

07h

POSTSCALE_B

PLL Post-scale Divider Select

PLL S/PDIF Receiver Mode

POSTSCALE_A is used to configure

a 256fs or 128fs PLLACLK,

POSTSCALE_B is not used. Refer

to Table 45.

PLL User Mode

Used in conjunction with the

FREQMODE_x bits. Refer to Table

44.

Table 43 Pre and Post PLL Clock Divider Control

f2 TO PLLxCLK DIVISION FACTOR

POSTSCALE_x

FREQMODE_x[1:0]

÷2

÷4

÷8

÷16

÷12

÷24

Table 44 PLL User Mode Clock Divider Configuration

POSTSCALE_A

PLLACLK FREQUENCY

256fs

128fs

Table 45 PLL S/PDIF Receiver Mode Clock Divider Configuration

WM8581 Datasheet(PDF) 53 Page - Wolfson Microelectronics plc

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