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WM8581 Datasheet(PDF) 57 Page - Wolfson Microelectronics plc |
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WM8581 Datasheet(HTML) 57 Page - Wolfson Microelectronics plc |
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57 / 100 page  Production Data WM8581 w PD Rev 4.0 April 2007 57 PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (HARDWARE MODE) In hardware mode, the user has no access to the internal clocking control registers and hence a default configuration is loaded at reset to provide maximum functionality. The S/PDIF receiver is enabled and hence the PLLs operate in S/PDIF receiver mode and all PLL and S/PDIF receiver control is fully automatic. All supported S/PDIF receiver sample rates can be used. FREQMODE_x and POSTSCALE_x control is fully automatic to ensure that the MCLK output is maintained at 256fs relative to the S/PDIF received sample rate. In hardware mode, the OSCCLK must be 12MHz and hence the external crystal (or applied XIN clock) must be 12MHz. No other OSCCLK frequencies are supported in hardware mode. |
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