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WM9713LGEFL/V Datasheet(PDF) 24 Page - Wolfson Microelectronics plc |
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WM9713LGEFL/V Datasheet(HTML) 24 Page - Wolfson Microelectronics plc |
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24 / 108 page  WM9713L Pre-Production w PP Rev 3.0 June 2006 24 CONTROL The register bits controlling PCM audio format, word length and operating modes are summarised below. CTRL must be set to override the normal use of the PCM interface pins as GPIOs, MODE must be set to specify master/slave modes. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 15 CTRL 0 Sets function and control registers for GPIO / PCM interface pins. 0 = GPIO pins as GPIOs 1 = GPIO pins configured as PCM interface and controlled by this register 14:13 MODE 10 PCM interface mode when CTRL=1 00 = PCM interface disabled [PCMCLK tri- stated, PCMFS tri-stated] 01 = PCM interface in slave mode [PCMCLK as input, PCMFS as input] 10 = PCM interface in master mode [PCMCLK as output, PCMFS as output] 11 = PCM interface in partial master mode [PCMCLK as output, PCMFS as input] 11:9 DIV 010 Voice DAC clock to PCMCLK divider. In master mode PCMCLK is derived from Voice DAC clock. 000 : PCMCLK = Voice DAC clock 001 : PCMCLK = Voice DAC clock / 2 010 : PCMCLK = Voice DAC clock / 4 011 : PCMCLK = Voice DAC clock / 8 100 : PCMCLK = Voice DAC clock / 16 8 VDACOS R 1 VXDAC oversample rate: 0: 128 x fs 1: 64 x fs 7 CP 0 PCMCLK polarity 1 = invert PCMCLK polarity 0 = normal PCMCLK polarity 6 FSP 0 Right, Left and I 2S modes – PCMFS polarity 1 = invert PCMFS polarity 0 = normal PCMFS polarity DSP Mode – mode A/B select 0 = MSB is available on 2nd PCMCLK rising edge after LRC rising edge (mode A) 1 = MSB is available on 1st PCMCLK rising edge after LRC rising edge (mode B) 36h PCM Control 5:4 SEL 10 PCM ADC channel select 00 = Output left and right ADC data 01 = Swap and output left and right ADC data 10 = Output left ADC data only 11 = Output right ADC data only |
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