AMC131M02DFMR datasheet(38/89 Pages) TI

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8.4.7 Power Modes

In both continuous-conversion and global-chop mode, there are two selectable power modes that allow scaling

of power with bandwidth and performance: high-resolution (HR) mode and low-power (LP) mode. The mode

is selected by the PWR[1:0] bits in the CLOCK register. Changing the PWR[1:0] bits scales the internal

bias currents to achieve the expected power levels. See the Recommended Operating Conditions table for

restrictions on the CLKIN frequency for each power mode.

8.4.8 Standby Mode

Standby mode is a low-power state in which all channels are disabled, and the reference and other non-essential

circuitry are powered down. This mode differs from completely powering down the device because the device

retains the register settings. Set the DCDC_EN bit in the DCDC_CTRL register to 0b to disable the DC/DC

converter before entering standby mode. Enter standby mode by sending the STANDBY command (0022h).

Stop toggling CLKIN when the device is in standby mode to minimize device power consumption. Exit standby

mode by sending the WAKEUP command (0033h).

8.5 Programming

8.5.1 Serial Interface

The AMC131M02 uses an SPI-compatible interface to configure the device and retrieve conversion data. The

device always acts as an SPI peripheral; SCLK and CS are inputs to the interface. The interface operates in SPI

mode 1, where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are launched or changed

only on SCLK rising edges; data are latched or read by the controller and peripheral on SCLK falling edges.

The interface is full-duplex, meaning data can be sent and received simultaneously by the interface. The device

includes the typical SPI signals: SCLK, CS, DIN, and DOUT. In addition, there are two other digital pins that

provide functionality. The DRDY pin serves as a flag to the host to indicate new conversion data are available.

The SYNC/RESET pin is a dual-function pin that allows synchronization of conversions to an external event and

allows for a hardware device reset.

8.5.1.1 Chip Select (CS)

The CS pin is an active low input signal that selects the device for communication. The device ignores any

communication and DOUT is high impedance when CS is held high. Hold CS low for the duration of a

communication frame to ensure proper communication. The interface is reset each time CS is taken high.

8.5.1.2 Serial Data Clock (SCLK)

The SCLK pin is an input that serves as the serial clock for the interface. Output data on the DOUT pin

transitions on the rising edge of SCLK and input data on DIN are latched on the falling edge of SCLK.

8.5.1.3 Serial Data Input (DIN)

The DIN pin is the peripheral in, controller out (PICO) pin for the device. Serial commands are shifted in through

the DIN pin by the device with each SCLK falling edge when the CS pin is low.

8.5.1.4 Serial Data Output (DOUT)

The DOUT pin is the peripheral out, controller in (POCI) pin for the device. The device shifts out command

responses and ADC conversion data serially with each rising SCLK edge when the CS pin is low. This pin

assumes a high-impedance state when CS is high.

8.5.1.5 Data Ready (DRDY)

The DRDY pin is an active-low output that indicates when new conversion data are ready in conversion mode.

Connect the DRDY pin to an input on the host to trigger periodic data retrieval in conversion mode. The period

between each DRDY falling edge is the data rate period.

The timing of DRDY with respect to the sampling of a given channel on the AMC131M02 depends on the

phase calibration setting of the channel and the state of the DRDY_SEL[1:0] bits in the MODE register. Setting

the DRDY_SEL[1:0] bits to 00b configures DRDY to assert when the channel with the largest positive phase

calibration setting, or the most lagging, has a new conversion result. When the bits are 01b, the device asserts

AMC131M02

SBASA56 – SEPTEMBER 2023

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