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ATMEGA64-16AI Datasheet(PDF) 46 Page - ATMEL Corporation

Part # ATMEGA64-16AI
Description  8-bit Microcontroller with 64K Bytes In-System Programmable Flash
PDF  393 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATMEGA64-16AI Datasheet(HTML) 46 Page - ATMEL Corporation

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46
ATmega64(L)
2490L–AVR–10/06
Power Management
and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby
saving power. The AVR provides various sleep modes allowing the user to tailor the
power consumption to the application’s requirements.
To enter any of the six sleep modes, the SE-bit in MCUCR must be written to logic one
and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the
MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down,
Power-save, Standby, or Extended Standby) will be activated by the SLEEP instruction.
See Table 17 for a summary. If an enabled interrupt occurs while the MCU is in a sleep
mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the
start-up time, it executes the interrupt routine, and resumes execution from the instruc-
tion following SLEEP. The contents of the Register File and SRAM are unaltered when
the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes
up and executes from the Reset Vector.
Figure 18 on page 37 presents the different clock systems in the ATmega64, and their
distribution. This figure is helpful in selecting an appropriate sleep mode.
MCUCR – MCU Control
Register
The MCU Control Register contains control bits for power management.
• Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the
SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is
the programmers purpose, it is recommended to write the Sleep Enable (SE) bit to one
just before the execution of the SLEEP instruction and to clear it immediately after wak-
ing up.
• Bits 4..2 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the six available sleep modes as shown in Table 17.
Note:
1. Standby mode and Extended Standby mode are only available with external crystals
or resonators.
Bit
7654
321
0
0x35 (0x55)
SRE
SRW10
SE
SM1
SM0
SM2
IVSEL
IVCE
MCUCR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0000
000
0
Table 17. Sleep Mode Select
SM2
SM1
SM0
Sleep Mode
000
Idle
0
0
1
ADC Noise Reduction
010
Power-down
011
Power-save
100
Reserved
101
Reserved
110
Standby(1)
1
1
1
Extended Standby(1)



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