ATMEGA640 datasheet(28/449 Pages) ATMEL

28 / 449 page

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

Pull-up and Bus-keeper

The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is

written to one. To reduce power consumption in sleep mode, it is recommended to dis-

able the pull-ups by writing the Port register to zero before entering sleep.

The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper

can be disabled and enabled in software as described in “XMCRB – External Memory

Control Register B” on page 36. When enabled, the bus-keeper will keep the previous

value on the AD7:0 bus while these lines are tri-stated by the XMEM interface.

Timing

External Memory devices have different timing requirements. To meet these require-

ments, the XMEM interface provides four different wait-states as shown in Table 8. It is

important to consider the timing specification of the External Memory device before

selecting the wait-state. The most important parameters are the access time for the

external memory compared to the set-up requirement. The access time for the External

Memory is defined to be the time from receiving the chip select/address until the data of

this address actually is driven on the bus. The access time cannot exceed the time from

the ALE pulse must be asserted low until data is stable during a read sequence (See

LLRL+ tRLRH - tDVRH in Tables 173 through Tables 180 on pages 385 - 387). The different

wait-states are set up in software. As an additional feature, it is possible to divide the

external memory space in two sectors with individual wait-state settings. This makes it

possible to connect two different memory devices with different timing requirements to

the same XMEM interface. For XMEM interface timing details, please refer to Table 173

to Table 180 and Figure 163 to Figure 166 in the “External Data Memory Timing” on

page 385.

Note that the XMEM interface is asynchronous and that the waveforms in the following

figures are related to the internal system clock. The skew between the internal and

external clock (XTAL1) is not guarantied (varies between devices temperature, and sup-

ply voltage). Consequently, the XMEM interface is not suited for synchronous operation.

Figure 15. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the

next instruction accesses the RAM (internal or external).

ALE

A15:8

Address

Prev. addr.

DA7:0

Address

Data

Prev. data

DA7:0 (XMBK = 0)

Data

Prev. data

Address

Data

Prev. data

Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

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ATMEGA640 Datasheet(PDF) 28 Page - ATMEL Corporation

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