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6.11.5.12 Octal Serial Peripheral Interface (OSPI)

OSPI0 offers two data capture modes, PHY mode and Tap mode.

PHY mode uses an internal reference clock to transmit and receive data via a DLL based PHY, where each

reference clock cycle produces a single cycle of OSPI0_CLK for Single Data Rate (SDR) transfers or a half

cycle of OSPI0_CLK for Double Data Rate (DDR) transfers. PHY mode supports three clocking topologies

for the receive data capture clock. Internal PHY Loopback - uses the internal reference clock as the PHY

receive data capture clock. Internal Pad Loopback - uses OSPI0_LBCLKO looped back into the PHY from the

OSPI0_LBCLKO pin as the PHY receive data capture clock. DQS - uses the DQS output from the attached

device as the PHY receive data capture clock. SDR transfers are not supported when using the Internal

Pad Loopback and DQS clocking topologies. DDR transfers are not supported when using the Internal PHY

Loopback or Internal Pad Loopback clocking topologies.

Tap mode uses an internal reference clock with selectable taps to adjusted data transmit and receive capture

delays relative to OSPI0_CLK, which is a divide by 4 of the internal reference clock for SDR transfers or a divide

by 8 of the internal reference clock for DDR transfers. Tap mode only supports one clocking topology for the

receive data capture clock. No Loopback - uses the internal reference clock as the Tap receive data capture

clock. This clocking topology supports a maximum internal reference clock rate of 200 MHz, which produces an

OSPI0_CLK rate up to 50 MHz for SDR mode or 25 MHz for DDR mode.

For more details about features and additional description information on the device Octal Serial Peripheral

Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

OSPI PHY Mode defines timing requirements and switching characteristics associated with PHY mode and

OSPI Tap Mode defines timing requirements and switching characteristics associated with Tap mode.

OSPI Timing Conditions presents timing conditions for OSPI0.

For more information, see Octal Serial Peripheral Interface (OSPI) section in the device TRM.

6.11.5.12.1 OSPI Timing Conditions

PARAMETER

MODE

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

V/ns

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of OSPI0_CLK

trace

No Loopback

Internal PHY Loopback

Internal Pad Loopback

450

Propagation delay of OSPI0_DQS

trace

DQS

L(1) - 30

L(1) + 30

td(Trace Mismatch

Delay)

Propagation delay mismatch of

OSPI0_D[7:0] and OSPI0_CSn[1:0]

relative to OSPI0_CLK

All modes

(1)

L = Propagation delay of OSPI0_CLK trace

6.11.5.12.2 OSPI PHY Mode

6.11.5.12.2.1 OSPI0 With PHY Data Training

Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating

frequency. A data training method may be implemented to dynamically configure optimal read and write timing.

Implementing data training enables proper operation across temperature with a specific process, voltage, and

frequency operating condition, while achieving a higher operating frequency.

TI Information - Selective Disclosure

www.ti.com

AM263P4, AM263P2, AM263P1, AM263P4-Q1, AM263P2-Q1, AM263P1-Q1

SPRSP81 – OCTOBER 2023

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