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AM263P4 Datasheet(PDF) 120 Page - Texas Instruments |
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AM263P4 Datasheet(HTML) 120 Page - Texas Instruments |
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120 / 154 page  tO22t O21 OSPI_DQS OSPI_D[i:0] Figure 6-35. OSPI0 Timing Requirements – PHY SDR with External Board Loopback 6.11.5.12.2.2.1.3 OSPI Switching Characteristics - PHY SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O7 tc(CLK) Cycle time, OSPI0_CLK 3.3V 6.03 ns O8 tw(CLKL) Pulse duration, OSPI0_CLK low 0.475P(1) - 0.3 ns O9 tw(CLKH) Pulse duration, OSPI0_CLK high 0.475P(1) - 0.3 ns O10 td(CSn-CLK) Delay time, OSPI0_CSn[1:0] active edge to OSPI0_CLK rising edge TBD TBD ns O11 td(CLK-CSn) Delay time, OSPI0_CLK rising edge to OSPI0_CSn[1:0] inactive edge TBD TBD ns O12 td(CLK-D) Delay time, OSPI0_CLK active edge to OSPI0_D[7:0] transition 3.3V TBD TBD ns (1) P = CLK cycle time = SCLK period in ns tO9t tO8t tO7t tO11t O12 O10 OSPI_CSn OSPI_CLK OSPI_D[i:0] Figure 6-36. OSPI0 Switching Characteristics – PHY SDR 6.11.5.12.2.2.2 OSPI0 PHY DDR Timing 6.11.5.12.2.2.2.1 OSPI DLL Delay Mapping for PHY DDR Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE Transmit 3.3V PHY_CONFIG_TX_DLL_DELAY_FLD TBD Receive 3.3V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD TBD All other modes PHY_CONFIG_RX_DLL_DELAY_FLD TBD 6.11.5.12.2.2.2.2 OSPI Timing Requirements - PHY DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O15 tsu(D-LBCLK) Setup time, OSPI0_D[7:0] valid before active OSPI0_DQS edge 3.3V, DDR with DQS TBD ns TI Information - Selective Disclosure AM263P4, AM263P2, AM263P1, AM263P4-Q1, AM263P2-Q1, AM263P1-Q1 SPRSP81 – OCTOBER 2023 www.ti.com 120 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated |
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