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AM263P4 Datasheet(PDF) 121 Page - Texas Instruments |
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AM263P4 Datasheet(HTML) 121 Page - Texas Instruments |
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121 / 154 page  NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O16 th(LBTCLK-D) Hold time, OSPI0_D[7:0] valid after active OSPI0_DQS edge 3.3V, DDR with DQS TBD ns tO16t tO16t O15 O15 OSPI_DQS OSPI_D[i:0] Figure 6-37. OSPI0 Timing Requirements – PHY DDR with External Board Loopback or DQS 6.11.5.12.2.2.2.3 OSPI Switching Characteristics - PHY DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O1 tc(CLK) Cycle time, OSPI0_CLK 19 ns O2 tw(CLKL) Pulse duration, OSPI0_CLK low 0.475P(1) - 0.3 ns O3 tw(CLKH) Pulse duration, OSPI0_CLK high 0.475P(1) - 0.3 ns O4 td(CSn-CLK) Delay time, OSPI0_CSn[1:0] active edge to OSPI0_CLK rising edge TBD TBD ns O5 td(CLK-CSn) Delay time, OSPI0_CLK rising edge to OSPI0_CSn[1:0] inactive edge TBD TBD ns O6 td(CLK-D) Delay time, OSPI0_CLK active edge to OSPI0_D[7:0] transition 3.3V TBD TBD ns (1) P = OSPI0_CLK cycle time = SCLK period in ns tO4t tO3t tO5t tO2t tO1t O6 O6 OSPI_CSn OSPI_CLK OSPI_D[i:0] Figure 6-38. OSPI0 Switching Characteristics – PHY DDR 6.11.5.12.3 OSPI Tap Mode 6.11.5.12.3.1 OSPI0 Tap SDR Timing 6.11.5.12.3.1.1 OSPI Timing Requirements - Tap SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O19 tsu(D-CLK) Setup time, OSPI0_D[7:0] valid before active OSPI0_CLK edge No Loopback 10.4 - (0.975 × T(1) × R(2)) ns O20 th(CLK-D) Hold time, OSPI0_D[7:0] valid after active OSPI0_CLK edge No Loopback 0.7 + (0.975 × T(1) × R(2)) ns (1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD] TI Information - Selective Disclosure www.ti.com AM263P4, AM263P2, AM263P1, AM263P4-Q1, AM263P2-Q1, AM263P1-Q1 SPRSP81 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 121 |
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