9.4 Layout

9.4.1 Layout Guidelines

1. Place supply bypass capacitors as close to VDD1V8 and VDD3V3 pins as possible and avoid placing the

bypass caps near the eDP/eDN and DP/DN traces.

2. Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections

and impedance changes. When a via must be used, increase the clearance size around it to minimize its

capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of

picking up interference from the other layers of the board. Be careful when designing test points on twisted

pair lines; through-hole pins are not recommended.

3. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This

reduces reflections on the signal traces by minimizing impedance discontinuities.

4. Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,

mounting holes, magnetic devices or ICs that use or duplicate clock signals.

5. Avoid stubs on the high-speed USB signals due to signal reflections. If a stub is unavoidable, then the stub

must be less than 200 mil.

6. Route all high-speed USB signal traces over continuous GND planes, with no interruptions.

7. Avoid crossing over anti-etch, commonly found with plane splits.

8. Due to high frequencies associated with the USB, a printed circuit board with at least four layers is

recommended; two signal layers separated by a ground and power layer as shown in Figure 9-3.

Signal 1

GND Plane

Power Plane

Signal 2

Figure 9-3. Four-Layer Board Stack-Up

TUSB2E22

SNLS648B – FEBRUARY 2019 – REVISED OCTOBER 2023

www.ti.com

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