ISL51002 datasheet(28/32 Pages) INTERSIL

28 / 32 page

December 22, 2006

Crystal Oscillator

An external 12MHz to 27MHz crystal supplies the low-jitter

reference clock to the DPLL. The absolute frequency of this

crystal within this range is unimportant, as is the crystal’s

temperature coefficient, allowing use of less expensive,

lower-grade crystals.

As an alternative to a crystal, the XTALIN pin can be driven

with a 3.3V CMOS-level external clock source at any

frequency between 12MHz and 27MHz. The ISL51002’s

jitter specification assumes a low-jitter crystal source. If the

external clock source has increased jitter, the sample clock

generated by the DPLL may exhibit increased jitter as well.

EMI Considerations

There are two possible sources of EMI on the ISL51002:

Crystal oscillator.

The EMI from the crystal oscillator is negligible. This is due to

an amplitude-regulated, low voltage sine wave oscillator circuit,

instead of the typical high-gain square wave inverter-type

oscillator, so there are no harmonics. The crystal oscillator is

not a significant source of EMI.

Digital output switching.

This is the largest potential source of EMI. However, the EMI is

determined by the PCB layout and the loading on the databus.

The way to control this is to put series resistors on the output of

all the digital pins (as our demo board and reference circuits

show). These resistors should be as large as possible, while

still meeting the setup and hold timing requirements of the

scaler. We recommend starting with 22

Ω. If the databus is

heavily loaded (long traces, many other part on the same bus),

this value may need to be reduced. If the databus is lightly

loaded, it may be increased.

Intersil’s recommendations to minimize EMI are:

• Minimize the databus trace length

• Minimize the databus capacitive loading.

If EMI is a problem in the final design, increase the value of the

digital output series resistors to reduce slew rates on the bus.

This can only be done as long as the scaler’s setup and hold

timing requirements continue to be met.

Standby Mode

The ISL51002 can be placed into a low power standby mode

by writing a 0x0F to register 0x2C, powering down the triple

ADCs, the DPLL, and most of the internal clocks.

To allow input monitoring and mode detection during power-

down, the following blocks remain active:

• Serial interface (including the crystal oscillator) to enable

• Activity and polarity detect functions (registers 0x01 and

0x02)

• The HSYNCOUT and VSYNCOUT pins (for mode detection)

Initialization

The ISL51002 initializes with default register settings for an

AC-coupled, RGB input on the VGA1 channel, with a 30-bit

output.

Reset

The ISL51002 has a Power On Reset (POR) function that

resets the chip to its default state when power is initially

applied, including resetting all the registers to their default

settings as described in the Register Listing. The POR

function takes 512k Crystal clocks (~21ms at 25MHz) to

complete. The external RESET pin duplicates the reset

function of the POR without having to cycle the power

supplies. The RESET pin does not need to be used in

normal operation and can be tied high.

ISL51002 Serial Communication

Overview

The ISL51002 uses a 2-wire serial bus for communication

with its host. SCL is the Serial Clock line, driven by the host,

and SDA is the Serial Data line, which can be driven by all

devices on the bus. SDA is open drain to allow multiple

devices to share the same bus simultaneously.

Communication is accomplished in three steps:

The Host selects the ISL51002 it wishes to communicate

with.

The Host writes the initial ISL51002 Configuration

The Host writes to or reads from the ISL51002’s

Configuration Register. The ISL51002’s internal address

pointer auto increments, so to read registers 0x00 through

0x1B, for example, one would write 0x00 in step 2, then

repeat step three 28 times, with each read returning the

next register value.

The ISL51002 has a 7-bit address on the serial bus. The

upper 6-bits are permanently set to 100110, with the lower

bit determined by the state of pin 67. This allows two

ISL51002s to be independently controlled while sharing the

same bus.

The bus is nominally inactive, with SDA and SCL high.

Communication begins when the host issues a START

command by taking SDA low while SCL is high (Figure 3).

The ISL51002 continuously monitors the SDA and SCL lines

for the start condition and will not respond to any command

until this condition has been met. The host then transmits the

7-bit serial address plus a R/W bit, indicating if the next

transaction will be a Read (R/W = 1) or a Write (R/W = 0). If

the address transmitted matches that of any device on the

bus, that device must respond with an ACKNOWLEDGE

(Figure 4).

ISL51002

ISL51002 Datasheet(PDF) 28 Page - Intersil Corporation

ISL51002 Datasheet(HTML) 28 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL