ISL51002 datasheet(6/32 Pages) INTERSIL

Part #	ISL51002

Description	10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features

PDF	32 Pages

Scroll/Zoom	100%

Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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6 / 32 page

December 22, 2006

Timing Diagrams

Data Output Setup and Hold Timing

RGB Output Data Timing and Latency

YUV Output Data Timing and Latency

PIXEL DATA

DATACLK

tHOLD

tSETUP

DATACLK

PROGRAMMABLE

WIDTH AND POLARITY

ANALOG

VIDEO IN

R/G/B[9:0]

HSOUT

8 DATACLK PIPELINE LATENCY

P10

P11

P12

HSYNCIN

THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED

TO. THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST

OF THE AFE’S OUTPUT SIGNALS

DATACLK

PROGRAM MABLE

W IDTH AND POLARITY

ANALOG

VIDEO IN

HSOUT

8 DATACLK PIPELINE LATENCY

P10

P11

P12

HSYNCIN

THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO.

THE SAM PLING PHASE SETTING DETERM INES ITS RELATIVE POSITION TO THE REST OF THE

AFE’S OUTPUT SIGNALS

DATACLK

G0 (YO) G1 (Y1)G2 (Y2)

B0 (UO)R0 (V0)B2 (U2)

G[9:0]

R[9:0]

B[9:0]

G3 (Y3)

R2 (V2)

ISL51002

ISL51002 Datasheet(PDF) 6 Page - Intersil Corporation

ISL51002 Datasheet(HTML) 6 Page - Intersil Corporation

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