Data Sheet

LT8418

analog.com

Rev 0

12 of 19

THEORY OF OPERATION

The LT8418 is a 100V half-bridge GaN driver that integrates top, bottom gate drivers, VCC, BST, UV, and OV protection

control logic. It can be used in half bridges and full bridges. It is very flexible to support multiple topologies including

buck, boost, buck-boost, and a variety of applications, including data center power, class-D audio amplifier, and

motor drivers. In addition, the LT8418 employs a small-footprint WLCSP package, which can be used in different

applications requiring high-power density, high-frequency operation, small form factor, and low cost.

1.1. Chip Start-up, VCCUVLO/OVLO Protections

The LT8418 has an undervoltage lockout (UVLO) in the VCC drive power rail. When the VCC voltage is falling below the

threshold voltage of 3.35 V, both the TG and BG pins are turned off to prevent the GaN FETs from being falsely turned

on. When the VCC voltage rises above its UVLO threshold of 3.55V (with 200mV hysteresis voltage), the LT8418 is

activated after a 100µs wakeup time. After that, the LT8418 senses INT and INB signals, and controls TG and BG

outputs. Due to the charging time of the BST rail, TG is prohibited from turning on until the BST UV threshold of 3.35V

is reached. On the other hand, to protect the GaN FETs from overdrive voltage and gate damage, VCC OVLO

(overvoltage lockout) feature is integrated into the LT8418. When the VCCvoltage rises above 6.0V, VCCOV is triggered,

which turns off both TG and BG; until the VCC voltage falls below 5.8V, VCC OV is recovered and TG/BG starts to switch

again following INT and INB control signals.

1.2. Input Interface INT, INB

The input pins of the LT8418 are independently controlled with TTL input thresholds and can withstand voltages up

to 15V. This allows the inputs to be directly connected to the outputs of an analog PWM controller with up to 15V

power supply, eliminating the need for a buffer stage. The LT8418 input pins, INT and INB, are independent and TTL

logic compatible. The LT8418 provides a fast propagation delay of 10ns and maintains an excellent delay matching

of 2.5ns between the top and bottom channels, making it suitable for high-frequency switching operations. Both

driver input pins, INT and INB, have a default pull-down resistor of 200kΩ to prevent GaN FETs from false turn-on.

LT8418 does not implement an overlap protection. If both INT and INB are asserted, both the high-side and low-side

GaN FETs are turned on. Careful consideration must be applied to the input interface to avoid a possible shoot-

through condition.

1.3. Smart Bootstrap (BST) Switch and BST UVLO

During the dead time interval between TG turn-off to BG turn-on, or between BG turn-off to TG turn-on, the GaN

power switch demonstrates a high reverse conduction voltage of 2V ~ 3V from source to drain (even higher at high

conduction current), which can bring SW node down to –2V ~ –3V and leads to the overcharge of BST rail and

permanent gate damage of GaN power switch. In the LT8418, the smart BST switch consists of power switches that

can be fully controllable for BST charging or blocking. When the bottom switch is turned on and the switching node

voltage is close to ground level, the BST switch is turned on to start charging the BST capacitor. In this way, the

LT8418 is able to generate a well-balanced bootstrap voltage from VCC with a minimum dropout voltage, which

prevents GaN FETs from overcharge and gate damage, as well as achieves matched propagation delay between the

top and bottom drivers and maintains balanced gate drive strength. The LT8418 provides a bootstrap UVLO

protection to prevent GaN FETs from turn-on at an insufficient gate drive voltage. When the BST-SW rail falls below

3.1V, TG stops to turn on until the BST capacitor is replenished and the BST rail rises above 3.35V (250mV hysteresis),

and TG starts to switch again.

1.4. Split Gate Driver

The LT8418 also provides split gate drivers for both top and bottom power switches. Thus, turn-on and turn-off slew

rates of the top and bottom gate drivers are adjustable independently by connecting different values of gate resistors

at TGP, TGN, BGP, and BGN pins. Besides, the LT8418 integrates strong gate drivers with 0.6Ω pull-up resistance, 0.2Ω