Data Sheet

LT8418

analog.com

Rev 0

14 of 19

occurs once per cycle, it is proportional to the switching frequency. Unlike a pure capacitive load, a power GaN FET’s

gate capacitance seen by the driver output varies with its VGS voltage level (VCC in this case) during switching. For

simplicity, the gate power dissipation can be calculated using its gate charge QG. For identical GaN FETs on BG and

TG, the gate loss is:

Pgate = 2Q

G · VCC · fsw

(3)

The reverse recovery loss and forward bias power loss on the traditional bootstrap diode are avoided by using the

integrated BST switch. The BST switch loss is dominated by the conduction loss on its RDS(ON) while charging the

capacitor. Larger GaN FET gate capacitance requires more current to charge the BST capacitor, resulting in more

loss:

PBST = D · IBST

2

· RDS(ON),BST

(4)

where:

IBST is the BST operating current charging the top-side gate capacitance.

RDS(ON),BST is the on-resistance of the BST switch.

1.4. PCB Bypass and Grounding Guideline

The LT8418 requires proper bypassing on the VCC, BST-SW supplies due to its high-speed switching (nanoseconds)

and large AC currents. Careless component placement and PCB routing may cause excessive ringing and

undershoots/overshoots.

To obtain the optimum performance from the LT8418:



Mount the capacitors as close as possible between the VCC and GND pins, and the BST and SW pins. The traces

should be shortened as much as possible to reduce lead inductance.



Use a low-inductance, low-impedance ground plane to reduce any ground drop and stray capacitance.

Remember that the LT8418 can sink up to 8A peak currents and any significant ground drop degrades signal

integrity.



Plan the power/ground routing carefully. Know where the large load switching current is coming from and

going. Maintain separate ground return paths for the input pin and output power stage.



Kelvin connect the TG pin to the top GaN FET gate and SW pin to the top GaN FET source. Kelvin connect the

BG pin to the bottom GaN FET gate and the driver ground to the bottom GaN FET source. Keep the copper

trace between the driver output pin and load short and wide.

1.5. Soldering Guideline

Precondition the solder pad with flux for better solder flow. Because of the small solder balls, type 4 solder paste (20

microns to 38 microns grain size) or finer solder paste is recommended to apply on the pad. After placing the IC

manually, a telescope should be used to ensure a good alignment. For better accuracy, it is recommended to use

automated fine-pitch placement machines with vision alignment. Melt the solder paste using a hot plate instead of

a heat gun to prevent the IC from being blown away. To verify good connections, vision inspection, and X-ray

inspection are recommended. Failure to make good electrical or thermal contact between the balls and the copper

board causes driver or system malfunction or higher thermal resistance.