PCM3060PWR datasheet(15/45 Pages) BURR-BROWN

15 / 45 page

www.ti.com

DEVICE DESCRIPTION

ASYNCHRONOUS OPERATION

SYSTEM CLOCK

w(SCH)

w(SCL)

2 V

0.8 V

T0005-14

(SCY)

System Clock

(SCK1,SCK2)

PCM3060

SLAS533 – MARCH 2007

The PCM3060 supports complete asynchronous operation between the ADC and DAC by receiving two

independent system clocks on SCKI1 and SCKI2.

Also, the PCM3060 supports synchronous operation between ADC and DAC by receiving one common system

clock on either SCKI1 or SCKI2 and controlling the system clock configuration through register 67 or 72 in serial

mode control.

The PCM3060 requires two system clocks for operating the ADC and DAC blocks independently, or it requires

one common clock for synchronous ADC and DAC operation.

The system clock for the ADC of the PCM3060 must be 256, 384, 512, or 768 fS, where fS is the audio sampling

rate for the ADC, 16 to 96 kHz.

The system clock for the DAC of the PCM3060 must be 128, 192, 256, 384, 512, or 768 fS, where fS is the audio

sampling rate for the DAC, 16 to 192 kHz.

Table 2 lists the typical system clock frequencies, fSCKI1 and fSCKI2 for common audio sampling rates, and

Figure 21 shows the timing requirements for the system clock inputs.

Table 2. System Clock Frequencies for Common Audio Sampling Clock Frequencies

SAMPLING

SYSTEM CLOCK FREQUENCY, fSCKI1, fSCKI2 [MHz]

FREQUENCY

128 fS(1)

192 fS(1)

256 fS

384 fS

512 fS

768 fS

(kHz)

2.048

3.072

4.096

6.144

8.192

12.288

4.096

6.144

8.192

12.288

16.384

24.576

44.1

5.6488

8.4672

11.2896

16.9344

22.5792

33.8688

6.144

9.216

12.288

18.432

24.576

36.864

88.2

11.2896

16.9344

22.5792

33.8688

See (2)

12.288

18.432

24.576

36.864

See (2)

176.4 (1)

22.5792

33.8688

See (2)

192 (1)

24.576

36.864

See (2)

(1)

This combination of sampling clock frequency and system clock frequency is supported only for the DAC.

(2)

This system clock frequency is not supported for the given sampling clock frequency.

SYMBOL

PARAMETERS

MIN

MAX

UNIT

t(SCY)

System clock cycle time

tw(SCH)

System clock high time

0.4 t(SCY)

tw(SCL)

System clock low time

0.4 t(SCY)

System clock duty cycle

40%

60%

Figure 21. System Clock Input Timing

Submit Documentation Feedback

PCM3060PWR Datasheet(PDF) 15 Page - Burr-Brown (TI)

PCM3060PWR Datasheet(HTML) 15 Page - Burr-Brown (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL