IP1201PBF datasheet(14/29 Pages) IRF

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iP1201PbF

Mode of Operation

The iP1201PbF can be configured to provide either two

independent dual outputs or single paralleled output with

current share. In dual output mode, the two error am-

plifiers of the PWM controller operate independently.

Each output voltage of the iP1201PbF block is con-

trolled by its own error amplifier. The output of the error

amplifier and the internally generated ramp signal are

compared to produce PWM pulses of fixed frequency

that drive the internal power switches. In this mode,

the VP-ref pin must be connected to Vref pin. Vref pin is

the internally generated 0.8V reference input of first er-

ror amplifier . Refer to the internal block diagram of the

iP1201PbF in Fig.1.

In single output mode, one error amplifier controls the

output voltage and the other amplifier monitors the in-

ductor current information for current sharing. In this

mode, VP-ref pin must be disconnected from Vref pin

and connected to the output of the inductor. See Fig.

17. The inductor current information is provided

through external shunts placed in series with the out-

put inductors.

A lossless inductor current sensing scheme can also

be implemented as shown in Fig. 18 where the cur-

rent is sensed throughthe DC resistance of the induc-

tor. In this case R

L and CL are selected such that RLx

L = L / Rdc. Set RL = 1K and solve for CL. Rdc is the

internal DC resistance of inductor L.

In single output mode, the iP1202 does not require a

soft start capacitor at SS2 pin.

The iP1201PbF can also be configured in dual output

tracking mode where the second output tracks the

first output.

For a specific output configuration, follow the con-

nection diagram shown in Fig.16, Fig.17 and Fig.18

at the end of this section.

Out of Phase Operation

The dual output PWM controller inside the iP1201PbF

provides a 180° out of phase operation of the PWM

outputs. This method of control offers the advan-

tage of reducing the amount of input bypass ca-

pacitors due to increase in input ripple frequency

and hence reduction of ripple amplitude. Moreover,

for paralleled output configurations 180° phase

shifting contributes to smaller output capacitors due

to output inductor ripple current cancellation and

ripple reduction.

The operating switching frequency (f

SW) range of

iP1201PbF is 200 kHz to 400 kHz. The desired fre-

quency is set by placing an external resistor to the RT

pin of the iP1201PbF. See Fig. 11 for the proper resis-

tor value.

The iP1201PbF is capable of accepting an external

digital synchronization signal. Synchronization will be

enabled by the rising edge clock. The free running

oscillator frequency is twice the per-channel fre-

quency. During synchronization, RT is selected such

that the free running frequency is 20% below the syn-

chronization frequency. The maximum synchroniza-

tion frequency that iP1201PbF can accept is 800kHz.

Note that the actual free running frequency of individual

output is half the synchronization frequency. Synchro-

nization capability is provided both in independent and

parallel configurations. When unused, the SYNC pin

must be left floating.

Overcurrent Protection/Autorestart

The Overcurrent Protection function of the iP1201PbF

offers two distinct modes: HICCUP of the output and

Overcurrent Shutdown. If the Hiccup pin is pulled high

(Hiccup enabled), hiccup mode will be selected. If Hic-

cup pin is pulled low (Hiccup dis- abled), overcurrent

shutdown will be selected.

During overloads, in HICCUP disabled mode, the

controller shuts down as soon as the trip threshold

is reached. In HICCUP enabled mode, when

overcurrent trip threshold is reached, the power

supply output shuts down and attempts to restart.

The time duration between the shutdown of the

output and the restart is determined by the time it

takes to discharge the soft start capacitor. Typically,

the discharge time of the soft start capacitor is 10

times the charge time. The duty cycle of the hiccup

process is typically 5%.The output will stay in hic-

cup indefinitely until the overload is removed. The

typical overcurrent trip threshold of the device is

internally set at 20A.

Overvoltage Protection (OVP)

Overvoltage is sensed through separate output volt-

age sense pins FB1s and FB2s. A separate OVP cir-

cuit is provided for each output and the OVP thresh-

old is set to 115% of the output voltage. Upon over-

voltage condition of either one of the outputs, the OVP

forces a latched shutdown on both outputs.

Frequency and Synchronization

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