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MP1048 Datasheet(PDF) 10 Page - Monolithic Power Systems

Part # MP1048
Description  Full Bridge CCFL Controller
PDF  12 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP1048 Datasheet(HTML) 10 Page - Monolithic Power Systems

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MP1048 – FULL BRIDGE CCFL CONTROLLER
MP1048 Rev. 0.9
www.MonolithicPower.com
10
9/24/2007
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
Pin 16 (BTR), Pin 23 (BTL), C8, C10:
BTR and BTL are the bias supplies for the level
shift of the upper MOSFETs. C8 and C10
should be 22nF and made of X7R ceramic
material.
Pin 19 (VCCR), Pin 26 (VCCL), C9, C11:
These capacitors bypass the gate supply for the
low-side switches. They also supply power to
the MP1048. These pins should be bypassed
with a 0.47µF ceramic X7R capacitor.
IMPORTANT–For all applications, VCCR and
VCCL must be connected together.
Pin 11 (DBRT):
This pin is used for burst brightness control.
The DC voltage on this pin will control the burst
percentage on the output. The signal is filtered
for optimal operation. A voltage ranging from 0V
to 1.2V on DBRT will correspond to a Burst
Duty
Cycle
of
the
minimum
to
100%
respectively.
For direct Pulse Width Modulation of the burst
signal, connect BRS to VCC and connect DBRT
with a logic level PWM signal. A logic High is
Burst On and a logic Low is Burst Off.
Pin 10 (BRS): C7, R6:
BRS is used to set the Burst Repetition Rate.
C7 and R6 will set the burst repetition rate and
the minimum burst time: tMIN. Set tMIN to achieve
the minimum required system brightness.
Ensure that tMIN is long enough that the lamp
does not extinguish.
These values are determined as follows:
Select a Minimum Duty Cycle, DMIN, where:
Burst
MIN
MIN
f
t
D
×
=
()
RISE
FALL
FALL
MIN
t
t
t
D
+
=
If operating in Free-Running mode:
b
V
P
MIN
I
2
V
V
Vbg
1
D
1
6
R
+
+
ξ
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
−
=
k
43
.
21
1
D
1
k
16
.
21
~
6
R
MIN
+
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
−
For DMIN=0.1 and R6=212kΩ
γ
×
×
−
=
6
R
f
D
1
7
C
b
MIN
For
DMIN=0.1,
R6=212k,
fb=200Hz,
then
C7=52nf:
Where
DMIN=Minimum Burst Duty Cycle,
Vbg=VP - VV (~1.2V), VP=peak BRS voltage
(~3.6V), VV = valley BRS voltage (~2.4V) and
fb=burst repetition rate.
405
.
0
4
.
2
6
.
3
ln
≈
⎟
⎠
⎞
⎜
⎝
⎛
=
γ
ESD Resistor
It is recommended that a resistor (RLI = 1kΩ) be
added in series with the lamp current feedback
as shown in Figure 4.
The addition of this resistor helps minimize the
possibility
of
ESD
damage
in
case
of
mishandling of the IC during board level
assembly and test.
MP1048
LI
Figure 4—ESD Resistor



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