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AS7221

I²C Master Interface

Datasheet

• PUBLIC

DS000479

• v4-00 • 2019-Jun-28

│ 26

8.4

Timing Characteristics

Figure 24 :

AS7221 I²C Master Timing Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCL

SCL Clock Frequency

400

kHz

tBUF

Bus Free Time Between a

STOP and START

1.3

µs

tHD:STA

Hold Time (Repeated)

START

0.6

µs

tLOW

LOW Period of SCL Clock

1.3

µs

tHIGH

HIGH Period of SCL Clock

0.6

µs

tSU:STA

Setup Time for a Repeated

START

0.6

µs

tHD:DAT

Data Hold Time

0.9

µs

tSU:DAT

Data Setup Time

100

Rise Time of Both SDA and

SCL

300

Fall Time of Both SDA and

SCL

300

tSU:STO

Setup Time for STOP

Condition

0.6

µs

Capacitive Load for Each

Bus Line

— total

capacitance of one

bus line in pF

400

CI/O

I/O Capacitance (SDA,

SCL)

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