TMD3725 datasheet(24/56 Pages) OSRAM

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Datasheet, Public

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[v2-00] 2023-Mar-21

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TMD3725 − Register Description

AIHTH Register (Address 0x87)

Figure 27:

AIHTH Register

The Clear (C) channel is compared against high-going 16-bit

threshold value set by AIHTL and AIHTH.

The contents of the AIHTH and AIHTL registers are combined

and treated as a sixteen bit threshold value. If the value

generated by the C channel is above the AIHTL/H threshold and

the APERS value is reached, the AINT bit is asserted. If AIEN is

set, then the INT pin will also assert.

When setting the 16-bit ALS threshold AIHTL must be written

first, immediately follow by AIHTH. Internally, the lower 8-bits

are buffered until the upper 8-bits are written. As the upper

8-bits are written both the high and low bytes are

simultaneously latched as a 16-bit value.

PILT Register (Address 0x88)

Figure 28:

PILT Register

The proximity channel is compared against low-going 8-bit

threshold value set by PILT.

If the value generated by the proximity channel is below the

PILT threshold and the PPERS value is reached, the PINT bit is

asserted. If PIEN is set, then the INT pin will also assert.

Addr: 0x87

AIHTH

Bit

Bit Name

Default

Access

Bit Description

7:0

AIHTH

0x00

This register sets the high byte of the HIGH ALS

threshold.

Addr: 0x88

PILT

Bit

Bit Name

Default

Access

Bit Description

7:0

PILT

0x00

This register sets the Proximity ADC channel low

threshold.

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