DSP56371 datasheet(7/68 Pages) FREESCALE

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DSP56371 Overview

DSP56371 Data Sheet, Rev. 4.1

Freescale Semiconductor

The PCU implements its functions using the following registers:

•

PC—program counter register

•

SR—Status register

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LA—loop address register

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LC—loop counter register

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VBA—vector base address register

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SZ—stack size register

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SP—stack pointer

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OMR—operating mode register

•

SC—stack counter register

The PCU also includes a hardware system stack (SS).

2.4.4

Internal Buses

To provide data exchange between blocks, the following buses are implemented:

•

Peripheral input/output expansion bus (PIO_EB) to peripherals

•

Program memory expansion bus (PM_EB) to program memory

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X memory expansion bus (XM_EB) to X memory

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Y memory expansion bus (YM_EB) to Y memory

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Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU and PCU, as well

as the memory-mapped registers in the peripherals

•

DMA data bus (DDB) for carrying DMA data between memories and/or peripherals

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DMA address bus (DAB) for carrying DMA addresses to memories and peripherals

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Program Data Bus (PDB) for carrying program data throughout the core

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X memory Data Bus (XDB) for carrying X data throughout the core

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Y memory Data Bus (YDB) for carrying Y data throughout the core

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Program address bus (PAB) for carrying program memory addresses throughout the core

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X memory address bus (XAB) for carrying X memory addresses throughout the core

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Y memory address bus (YAB) for carrying Y memory addresses throughout the core

All internal buses on the DSP56300 family members are 24-bit buses. See Figure 1.

2.4.5

Direct Memory Access (DMA)

The DMA block has the following features:

•

Six DMA channels supporting internal and external accesses

•

One-, two- and three-dimensional transfers (including circular buffering)

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End-of-block-transfer interrupts

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