DSP56371 datasheet(2/68 Pages) FREESCALE

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DSP56371 Data Sheet, Rev. 4.1

DSP56371 Overview

Freescale Semiconductor

the DSP56300 family of programmable CMOS DSPs. The DSP56371 is targeted to applications that

require digital audio compression/decompression, sound field processing, acoustic equalization and other

digital audio algorithms. Changes in core functionality specific to the DSP56371 are also described in this

manual. See Figure 1. for the block diagram of the DSP56371.

Figure 1. DSP56371 Block Diagram

2.2

DSP56300 Core Description

The DSP56371 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that

provides up to twice the performance of Motorola's popular DSP56000 core family while retaining code

compatibility with it.

PLL

OnCE™

Clock

Gen-

erator

YAB

XAB

PAB

YDB

XDB

PDB

GDB

MODB/IRQB

MODC/IRQC

MODD/IRQD

DSP56300

24-Bit

DDB

DAB

Peripheral

Core

Expansion Area

JTAG

RESET

MODA/IRQA

PINIT/NMI

EXTAL

Address

Generation

Unit

Six Channel

DMA Unit

Program

Interrupt

Controller

Program

Decode

Controller

Program

Address

Generator

Data ALU

× 24+56→56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

Power

Mgmt.

Memory Expansion Area

X Data

RAM

36K

× 24

Y Data

RAM

48K

× 24

Bootstrap

ROM

Internal

Data

Bus

Switch

SHI

Triple

ESAI

ESAI_1

EFCOP

Interface

Timer

Interface Interface

GPIO

ROM

32K

× 24

ROM

32K

× 24

Program

RAM

× 24

ROM

64K

× 24

DAX

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