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DSP56371 Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc |
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DSP56371 Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc |
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13 / 68 page ![]() Signal/Connection Descriptions DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 13 3.2 Power Figure 3. VDD Connections Table 2. Power Inputs Power Name Description PLLA_VDD (1) PLLP_VDD(1) PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate external decoupling capacitors. PLLD_VDD (1) PLL Power— The voltage (1.25 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate external decoupling capacitors. CORE_VDD (4) Core Power—The voltage (1.25 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate decoupling capacitors. IO_VDD (5) SHI, ESAI, ESAI_1, DAX and Timer I/O Power —The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. This is an isolated power for the SHI, ESAI, ESAI_1, DAX and Timer I/O. The user must provide adequate external decoupling capacitors. 60 FST_PE4 59 SDO5_SDI0_PE6 58 SDO4_SDI1_PE7 57 SDO3_SDI2_PE8 56 SDO2_SDI3_PE9 55 SDO1_PE10 54 SDO0_PE11 53 CORE_GND 52 CORE_VDD 51 MODB_IRQA 50 MODB_IRQB 49 MODC_IRQC 48 MODD_IRQD 47 RESET_B 46 PINIT_NMI 45 EXTAL 44 PLLD_VDD 43 PLLD_GND 42 PLLP_GND 41 PLLP_VDD SDO5_SDI0_PC7 1 IO_GND 2 IO_VDD 3 SDO3_SDI2_PC8 4 SDO2_SDI3_PC9 5 SDO1_PC10 6 SDO0_PC11 7 CORE_VDD 8 PF8 9 PF6 10 PF7 11 CORE_GND 12 PF2 13 PF3 14 PF4 15 PF5 16 IO_VDD 17 PF1 18 PF0 19 IO_GND 20 ESAI ESAI_1 DAX Int/Mod PLL SHI OnCE Timer GPIO 3.3V 1.25V |
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