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M68HC05 Datasheet(PDF) 64 Page - Freescale Semiconductor, Inc |
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M68HC05 Datasheet(HTML) 64 Page - Freescale Semiconductor, Inc |
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64 / 118 page ![]() Serial Communications Interface (SCI) MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 64 Freescale Semiconductor 9.11 Start Bit Detection When the input (idle) line is detected low, it is tested for three more sample times (referred to as the start edge verification samples in Figure 9-4). If at least two of these three verification samples detect a logic 0, a valid start bit has been detected; otherwise, the line is assumed to be idle. A noise flag is set if all three verification samples do not detect a logic 0. Thus, a valid start bit could be assumed with a set noise flag present. If a framing error has occurred without detection of a break (10 0s for 8-bit format or 11 0s for 9-bit format), the circuit continues to operate as if there actually was a stop bit, and the start edge will be placed artificially. The last bit received in the data shift register is inverted to a logic 1, and the three logic 1 start qualifiers (shown in Figure 9-4) are forced into the sample shift register during the interval when detection of a start bit is anticipated (see Figure 9-6); therefore, the start bit will be accepted no sooner than it is anticipated. If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $003B) produced the framing error, the start bit will not be artificially induced and the receiver must actually detect a logic 1 before the start bit can be recognized (see Figure 9-7). Figure 9-6. SCI Artificial Start Following a Frame Error Figure 9-7. SCI Start Bit Following a Break DATA EXPECTED STOP DATA SAMPLES ARTIFICIAL EDGE START BIT DATA RDI DATA EXPECTED STOP DATA SAMPLES START EDGE START BIT DATA RDI a) Case 1: Receive line low during artificial edge b) Case 2: Receive line high during expected start edge EXPECTED STOP DATA SAMPLES DETECTED AS VALID START EDGE START BIT RDI BREAK START QUALIFIERS START EDGE VERIFICATION SAMPLES |
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