ADN4604ASVZ datasheet(16/40 Pages) AD

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ADN4604

Data Sheet

Rev. A | Page 16 of 40

THEORY OF OPERATION

INTRODUCTION

The ADN4604 is a 16 × 16, buffered, asynchronous crosspoint

switch that provides input equalization, output preemphasis,

and output level programming capabilities. The receivers

integrate an equalizer that is optimized to compensate for

typical backplane losses. The switch supports multicast and

broadcast operation, allowing the ADN4604 to work in

redundancy and port-replication applications. The part offers

extensively programmable output levels and preemphasis

settings.

PRE-

EMPHASIS

16 × 16

SWITCH

MATRIX

CONNECTION

MAP 0

CONNECTION

MAP 1

SERIAL

INTERFACE

CONTROL

LOGIC

PER-PORT

OUTPUT

LEVEL

SETTINGS

OUTPUT

LEVEL

HOOKUP

TABLE

ADN4604

VCC

VEE

DVCC

OP[15:0]

VTTON,

VTTOS

ON[15:0]

IP[15:0]

VTTIE,

VTTIW

IN[15:0]

I2C/SPI

ADDR1/SDI

SDA/SDO

SCL/SCK

RESET

UPDATE

ADDR0/CS

Figure 39. Block Diagram

The configuration of the crosspoint is controlled through

a serial interface. This interface supports both I2C and SPI

protocols, which can be selected using the I2C /SPI dedicated

control pin. There are two I2C address pins available as

described in Table 6.

Table 6. Serial Interface Control Modes

No.

I2C/SPI = 0

I2C/SPI = 1

Name

Function

Name

Function

ADDR1

I2C Address

MSB

SDI

SPI Data

Input

ADDR0

I2C Address

LSB

SPI Chip

Select

SDA

I2C Data

SDO

SPI Data

Output

SCL

I2C Clock

SCK

SPI Clock

RECEIVERS

The ADN4604 receiver inputs incorporate 50 Ω termination

resistors, ESD protection, and an equalizer that is optimized for

operation over long backplane traces. Each receive channel also

provides a positive/negative (P/N) inversion function, which allows

the user to swap the sign of the input signal path to eliminate the

need for board-level crossovers in the receiver channel.

VCC

VTTIx

IPx

INx

VEE

SIMPLIFIED RECEIVER INPUT CIRCUIT

RLN

RLP

1kΩ

750Ω

52Ω

Figure 40. Simplified Input Circuit

Equalization

The ADN4604 receiver incorporates a continuous time equalizer

(EQ) that provides 12 dB of high frequency boost to compensate

up to 40 inches of FR4 at 4.25 Gbps. Each input has an equalizer

control bit. By default, the programmable boost is set to 12 dB.

The boost can be set to 0 dB by programming a Logic 0 to the

respective register bit for the corresponding channel.

Table 7. Equalization Control Registers

EQ[15:0]

Equalization Boost

0 dB

12 dB (default)

Lane Inversion

The receiver P/N inversion is a feature intended to allow the

user to implement the equivalent of a board-level crossover in

a much smaller area and without additional via impedance

discontinuities that degrade the high frequency integrity of the

signal path. The P/N inversion is available independently for

each of the 16 input channels and is controlled by writing to the

SIGN bit of the RX control registers (Addresses 0x12 and

Address 0x13). Note that using this feature to account for signal

inversions downstream of the receiver requires additional

attention when switching connectivity.

Table 8. Signal Path Polarity Control

SIGN[15:0]

Signal Path Polarity

Noninverting (default)

Inverting

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