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ADN8102ACPZ-R7 Datasheet(PDF) 31 Page - Analog Devices |
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ADN8102ACPZ-R7 Datasheet(HTML) 31 Page - Analog Devices |
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31 / 36 page ![]() ADN8102 Rev. C | Page 31 of 36 REGISTER MAP Table 22. I2C Register Definitions Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Reset 0x00 RESET Loopback control 0x02 LB[1] LB[0] 0x00 Control interface mode 0x0F MODE[1] MODE[0] 0x00 TxHeadroom 0x23 TxH_B3 TxH_B2 TxH_B1 TxH_B0 TxH_A3 TxH_A2 TxH_A1 TxH_A0 0x00 IN_A configuration 0x80 PNSWAP EQBY EN EQ[2] EQ[1] EQ[0] 0x30 IN_A LOS threshold 0x81 THRESH[6] THRESH[5] THRESH[4] THRESH[3] THRESH[2] THRESH[1] THRESH[0] 0x04 IN_A LOS hysteresis 0x82 HYST[6] HYST[5] HYST[4] HYST[3] HYST[2] HYST[1] HYST[0] 0x12 IN_A LOS status1 0x1F STICKY LOS[3] STICKY LOS[2] STICKY LOS[1] STICKY LOS[0] REAL-TIME LOS[3] REAL-TIME LOS[2] REAL-TIME LOS[1] REAL-TIME LOS[0] IN_A EQ1 control 0x83 EQ CTL SRC EQ1[5] EQ1[4] EQ1[3] EQ1[2] EQ1[1] EQ1[0] 0x00 IN_A EQ2 control 0x84 EQ2[5] EQ2[4] EQ2[3] EQ2[2] EQ2[1] EQ2[0] 0x00 IN_A0 FR4 control 0x85 LUT SELECT LUT FR4/CX4 0x00 IN_A1 FR4 control 0x8D LUT SELECT LUT FR4/CX4 0x00 IN_A2 FR4 control 0x95 LUT SELECT LUT FR4/CX4 0x00 IN_A3 FR4 control 0x9D LUT SELECT LUT FR4/CX4 0x00 IN_B configuration 0xA0 PNSWAP EQBY EN EQ[2] EQ[1] EQ[0] 0x30 IN_B LOS threshold 0xA1 THRESH[6] THRESH[5] THRESH[4] THRESH[3] THRESH[2] THRESH[1] THRESH[0] 0x04 IN_B LOS hysteresis 0xA2 HYST[6] HYST[5] HYST[4] HYST[3] HYST[2] HYST[1] HYST[0] 0x12 IN_B LOS Status1 0x3F STICKY LOS[3] STICKY LOS[2] STICKY LOS[1] STICKY LOS[0] REAL-TIME LOS[3] REAL-TIME LOS[2] REAL-TIME LOS[1] REAL-TIME LOS[0] IN_B EQ1 control 0xA3 EQ CTL SRC EQ1[5] EQ1[4] EQ1[3] EQ1[2] EQ1[1] EQ1[0] 0x00 IN_B EQ2 control 0xA4 EQ2[5] EQ2[4] EQ2[3] EQ2[2] EQ2[1] EQ2[0] 0x00 IN_B3 FR4 control 0xA5 LUT SELECT LUT FR4/CX4 0x00 IN_B2 FR4 Control 0xAD LUT SELECT LUT FR4/CX4 0x00 IN_B1 FR4 control 0xB5 LUT SELECT LUT FR4/CX4 0x00 IN_B0 FR4 control 0xBD LUT SELECT LUT FR4/CX4 0x00 |
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