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ADN8102ACPZ-R7 Datasheet(PDF) 10 Page - Analog Devices |
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ADN8102ACPZ-R7 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 36 page ![]() ADN8102 Rev. C | Page 10 of 36 50Ω CABLES 2 2 TP3 HIGH SPEED SAMPLING OSCILLOSCOPE 50Ω CABLES 2 2 50Ω ADN8102 AC-COUPLED EVALUATION BOARD INPUT PIN OUTPUT PIN PATTERN GENERATOR DATA OUT TP1 50Ω CABLES 2 2 TP2 FR4 TEST BACKPLANE DIFFERENTIAL STRIPLINE TRACES 8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT TRACE LENGTHS = 40'' 50ps/DIV REFERENCE EYE DIAGRAM AT TP1 Figure 10. Input Equalization Test Circuit, FR4 50ps/DIV Figure 11. 3.25 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 10) 50ps/DIV Figure 12. 3.75 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 10) 50ps/DIV Figure 13. 3.25 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting (TP3 from Figure 10) 50ps/DIV Figure 14. 3.75 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting (TP3 from Figure 10) |
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