AM79C940KCSLASHW datasheet(26/144 Pages) AMD

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Am79C940

HOST SYSTEM INTERFACE

DBUS15-0

Data Bus (Input/Output/3-state)

DBUS contains read and write data to and from internal

registers and the Transmit and Receive FIFOs.

ADD4-0

Address Bus (Input)

ADD is used to access the internal registers and FIFOs

to be read or written.

R/W

Read/Write (Input)

Indicates the direction of data flow during the MACE

device register, Transmit FIFO, or Receive FIFO

accesses.

RDTREQ

Receive Data Transfer Request(Output)

Receive Data Transfer Request indicates that there is

data in the Receive FIFO to be read. When RDTREQ

is asserted there will be a minimum of 16 bytes to be

read except at the completion of the frame, in which

case EOF will be asserted. RDTREQ can be pro-

grammed to request receive data transfer when 16, 32

or 64 bytes are available in the Receive FIFO, by pro-

gramming the Receive FIFO Watermark (RCVFW bits)

in the FIFO Configuration Control register. The first

assertion of RDTREQ will not occur until at least 64

bytes have been received, and the frame has been ver-

ified as non runt. Runt packets will normally be deleted

from the Receive FIFO with no external activity on

RDTREQ. When Runt Packet Accept is enabled (RPA

bit) in the User Test Register, RDTREQ will be asserted

when the runt packet completes, and the entire frame

resides in the Receive FIFO. RDTREQ will be asserted

only when Enable Receive (ENRCV) is set in the MAC

Configuration Control register.

The RCVFW can be overridden by enabling the Low

Latency Receive function (setting LLRCV bit) in the

Receive Frame Con trol re giste r, wh ich a llows

RDTREQ to be asserted after only 12 bytes have been

received. Note that use of this function exposes the

system interface to premature termination of the

receive frame, due to network events such as collisions

or runt packets. It is the responsibility of the system

designer to provide adequate recovery mechanisms for

these conditions.

TDTREQ

Transmit Data Transfer Request (Output)

Transmit Data Transfer Request indicates there is

room in the Transmit FIFO for more data. TDTREQ is

asserted when there are a minimum of 16 empty bytes

in the Transmit FIFO. TDTREQ can be programmed to

request transmit data transfer when 16, 32 or 64 bytes

are available in the Transmit FIFO, by programming the

Transmit FIFO Watermark (XMTFW bits) in the FIFO

Configuration Control register. TDTREQ will be

asserted only when Enable Transmit (ENXMT) is set in

the MAC Configuration Control register.

FDS

FIFO Data Select (Input)

FIFO Data Select allows direct access to the transmit

or Receive FIFO without use of the ADD address bus.

FDS must be activated in conjunction with R/W. When

the MACE device samples R/W as high and FDS low,

a read cycle from the Receive FIFO will be initiated.

When the MACE chip samples R/W and FDS low, a

write cycle to the Transmit FIFO will be initiated. The

CS line should be inactive (high) when FIFO access is

requested using the FDS pin. If the MACE device sam-

ples both CS and FDS as active simultaneously, no

cycle will be executed, and DTV will remain inactive.

DTV

Data Transfer Valid (Output/3-state)

When asserted, indicates that the read or write opera-

tion has completed successfully. The absence of DTV

at the termination of a host access cycle on the MACE

device indicates that the data transfer was unsuccess-

ful. DTV need not be used if the system interface can

guarantee that the latency to TDTREQ and RDTREQ

assertion and de-assertion will not cause the Transmit

FIFO to be over-written or the Receive FIFO to be

over-read. In this case, the latching or strobing of read

or write data can be synchronized to the SCLK input

rather than to the DTV output.

EOF

End Of Frame (Input/Output/3-state)

End Of Frame will be asserted by the MACE device

when the last byte/word of frame data is read from the

Receive FIFO, indicating the completion of the frame

data field for the receive message. End Of Frame must

be asserted low to the MACE device when the last

byte/word of the frame is written into the Transmit

FIFO.

BE1–0

Byte Enable (Input)

Used to indicate the active portion of the data transfer

to or from the internal FIFOs. For word (16-bit) trans-

fers, both BE0 and BE1 should be activated by the

external host/controller. Single byte transfers are per-

formed by identifying the active data bus byte and acti-

vating only one of the two signals. The function of the

BE1-0 pins is programmed using the BSWP bit (BIU

Configuration Control register, bit 6). BE1-0 are not

required for accesses to MACE device registers.

AM79C940KC/W Datasheet(PDF) 26 Page - Advanced Micro Devices

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