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AM79C940VC/W Datasheet(PDF) 107 Page - Advanced Micro Devices |
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AM79C940VC/W Datasheet(HTML) 107 Page - Advanced Micro Devices |
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107 / 144 page  107 DI± RXCRS IVCO SRDCLK (Note 1) BCC BCB Bit Cell (n–1) BCC BCB 10 Bit Cell (n) bit (n–1) bit (n) (Note 2) SRD VASQ 60 61 16235D-36 Notes: 1. RXCRS deasserts in less than 3 bit times after last DI ± rising edge. 2. Start of next packet reception (2 bit times). 3. IVCO is an internal signal shown for clarification only. AUI Receive Timing–End of Packet (Last Bit = 0) DI± RXCRS IVCO SRDCLK SRD (Note 1) BCC BCB Bit Cell (n–1) BCC 01 Bit Cell (n) bit (n–1) bit (n) 61 Notes: 1. RXCRS deassets in less than 3 bit times after last DI ± rising edge. 2. IVCO is an internal signal shown for clarification only. 16235D-37 AUI Receive Timing–End of Packet (Last Bit = 1) |
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