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STSLVDSP27 Datasheet(PDF) 9 Page - STMicroelectronics |
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STSLVDSP27 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 23 page ![]() STSLVDSP27 Electrical characteristics 9/23 Note: 1 50% VDIN to 50% VDOUT Table 7. Serial switching characteristics (DPLL = "OFF", RT = 100Ω ±1%, CL = 10pF, over recommended operating conditions unless otherwise noted. Typical values are referred to TA = 25°C and VDD = 3.0V, VIO = 1.8V) Symbol Parameter Test Conditions Min. Typ. Max. Unit trVOD Rise time differential output voltage (20% to 80%) (Figure 4.) trDIN = 4.9ns (10% to 90%); fDIN = 10MHz, PulseWidthDIN = 50ns 400 610 1000 ps tfVOD Fall time differential output voltage (80% to 20%) (Figure 4.) trDIN = 4.2ns (90% to 10%); fDIN = 10MHz, PulseWidthDIN = 50ns 400 610 1000 ps tPLHD Differential propagation delay time (DIN to DOUT) (Low to High) (Note: 1) (Figure 4.) trDIN = 4.9ns (10% to 90%); tfDIN = 4.2ns (90% to 10%); fDIN = 10MHz, PulseWidthDIN = 50ns 1.0 2.1 2.8 ns tPHLD Differential propagation delay time (DIN to DOUT) (Low to High) (Note: 1) (Figure 4.) tfDIN = 4.2ns (10% to 90%); fDIN = 10MHz, PulseWidthDIN = 50ns 1.0 2.1 2.8 ns tEN Enable delay time (EN to DOUT: tPLZ, tPHZ) (Figure 7.) trEN = 2.0ns (10% to 90%); tfEN = 2.0ns (90% to 10%) 20 µs tDIS Disable delay time (EN to DOUT: tPLZ, tPHZ) (Figure 7.) trEN = 2.0ns (10% to 90%); tfEN = 2.0ns (90% to 10%) 1000 ns fOPR Operating frequency serial mode without DPLL BYP = VDD trDIN0,CLKIN=1ns (10% to 90%); tfDIN0,CLKIN=1ns (90% to 10%) fDIN0,CLKIN = 208MHz PulseWidthDIN0,CLKIN = 2.4ns 1208 MHz tSKEW1 Differential skew between signals on each differential pair (tPLHD - tPHLD) trDIN = 4.9ns (10% to 90%); tfDIN = 4.2ns (90% to 10%); fDIN = 10MHz, PulseWidthDIN = 50ns 150 ps tSKEW2 Channel to channel skew between any two signals on each different differential pair (Figure 6.) trDIN = 4.9ns (10% to 90%); tfDIN = 4.2ns (90% to 10%); fDIN = 10MHz, PulseWidthDIN = 50ns 200 ps |
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