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STSLVDSP27 Datasheet(PDF) 11 Page - STMicroelectronics

Part # STSLVDSP27
Description  8-bit low voltage serializer with 1.8V high speed dual differential line drivers and embedded DPLL
PDF  23 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STSLVDSP27 Datasheet(HTML) 11 Page - STMicroelectronics

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STSLVDSP27
Electrical characteristics
11/23
Note:
1
50% VDIN to 50% VDOUT
2
50% CLKIN (positive edge) to 50% VDOUT (DIN0 will be referred to CLKOUT first positive
edge; DIN7 will be referred to CLKOUT eighth positive edge)
3
Power down can be guaranteed when VIO =1.8V, EN = GND, if low impedance < 1MΩ vs
GND is guaranteed on VDD pin
fCLKOUT
CLKOUT frequency
parallel mode with DPLL
BYP = GND, fDIN0-DIN7,CLKIN=4 to
27MHz PulseWidthDIN0,CLKIN = 50%
trDIN0,CLKIN=3ns (10% to 90%);
tfDIN0,CLKIN=3ns (90% to 10%)
32
216
MHz
tSKEW1
Differential skew between
signals on each differential
pair (tPLHD - tPHLD)
trDIN = 4.9ns (10% to 90%);
tfDIN = 4.2ns (90% to 10%);
fDIN = 10MHz, PulseWidthDIN = 50ns
150
ps
tSKEW2
Channel to channel skew
between any two signals
on each different
differential pair (Figure 6.)
trDIN = 4.9ns (10% to 90%);
tfDIN = 4.2ns (90% to 10%);
fDIN = 10MHz, PulseWidthDIN = 50ns
200
ps
tDV
Data valid before CLKOUT
time (Figure 12.)
BYP = GND, fDIN0-DIN7,CLKIN=4 to
27MHz PulseWidthDIN0,CLKIN = 50%
trDIN0,CLKIN=3ns (10% to 90%);
tfDIN0,CLKIN=3ns (90% to 10%)
1ns
tDH
Data valid hold after
CLKOUT time (Figure 12.)
BYP = GND, fDIN0-DIN7,CLKIN=4 to
27MHz PulseWidthDIN0,CLKIN = 50%
trDIN0,CLKIN=3ns (10% to 90%);
tfDIN0,CLKIN=3ns (90% to 10%)
2ns
tPLLS
DPLL settling time (EN to
CLKOUT) 50% LH EN to
50% CLKOUT (first
negative edge) (Figure 9.)
trEN =2.0ns (10% to 90%)
tfEN =2.0ns (90% to 10%)
DV0=DV1=VDD; BYP= Gnd; DIN1-
DIN7=VDD or Gnd;
fCLKIN =4 to 27MHz
70
µs
JCY-CY
RMS cycle-to-cycle jitter
between CLKIN and
CLKOUT signals
trCLKIN = 4.9ns (10% to 90%);
tfCLKIN = 4.2ns (90% to 10%);
fCLKIN = 4 to 27MHz,
PulseWidthCLKIN =50%
100
ps
Peak cycle-to-cycle jitter
between CLKIN and
CLKOUT signals
trCLKIN = 4.9ns (10% to 90%);
tfCLKIN = 4.2ns (90% to 10%);
fCLKIN = 4 to 27MHz,
PulseWidthCLKIN =50%
600
Table 8.
Parallel switching characteristics (DPLL = "ON", RT = 100Ω ±1%, CL = 10pF, over
recommended operating conditions unless otherwise noted. Typical values are referred to
TA = 25°C and VDD = 3.0V, VIO = 1.8V)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit



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