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VNF9D5F Datasheet(PDF) 26 Page - STMicroelectronics |
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VNF9D5F Datasheet(HTML) 26 Page - STMicroelectronics |
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26 / 106 page ![]() Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DATA2 0 0 0 0 0 0 0 Note: X = do not care. 0xBF - clear all status registers (RAM access) When an OpCode ‘10’ (read and clear operation) at address b’111111 is performed. Table 22. Clear all status registers (RAM access) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Command OC1 OC0 Address 1 0 1 1 1 1 1 1 DATA1 X X X X X X X 0 0 0 0 0 0 0 DATA2 X X X X X X X 0 0 0 0 0 0 0 Note: X = do not care. Note: Reset value = the value of the register after a power on. Default value = the default value of the register. Currently this is equivalent to the reset value. Cleared register = explicitly read and clear of the register, if it is not write-protected. 4.3 Register map The device contains a set of RAM registers used for device configuration, the device status and ROM registers for device identification. Since ST-SPI is used, Global Status byte defines the device status, containing fault information. 4.3.1 Global status byte description The data shifted out on SDO during each communication starts with a specific byte called global status byte. This one is used to inform the microcontroller about global faults which can happen at channel-side level (that is, like thermal shutdown...) or on the SPI interface (like watchdog monitoring timeout event, communication error, ...). This specific register has the following format: Table 23. Global Status Byte (GSB) MSB LSB GSBN RSTB SPIE TSD/PL ITLOFF LOFF TCASE FS Table 24. Global Status Byte Bit Name Reset Content 7 Global status bit not (GSBN) 0 The GSBN is a logically NOR combination of Bit 0 to Bit 6. This bit can also be used as Global Status Flag without starting a complete communication frame as it is present directly after pulling CSN low. 6 Reset bit (RSTB) 1 The RSTB indicates a device reset. In case this bit is set, all internal Control Registers are set to default and kept in that state until the bit is cleared. The reset bit is automatically cleared by any valid SPI communication VNF9D5F SPI functional description DS13946 - Rev 6 page 26/106 |
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