TDA8752 datasheet(24/36 Pages) PHILIPS

24 / 36 page

1999 Mar 09

Philips Semiconductors

Product speciﬁcation

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

GFINE

ﬁne gain correction range

ﬁne register input code = 0;

(see Fig.9)

−

ﬁne register input

code = 31; (see Fig.9)

−−0.5

−

∆Gamp/T

ampliﬁer gain stability as a

function of temperature

Vref = 2.5 V with

100 ppm/

°C maximum

variation

−−

200

ppm/

°C

IGC

gain current

−±20

−µA

tstab

ampliﬁer gain adjustment

speed

HSYNC active; capacitors

on pins 8, 16 and 24 = 22 nF

−

mdB/

µs

Vi(p-p)

input voltage range

(peak-to-peak value)

corresponding to full-scale

output

0.4

−

1.2

tr(Vi)

input voltage rise time

fi = 100 MHz; square wave

−−

2.5

tf(Vi)

input voltage fall time

fi = 100 MHz; square wave

−−

2.5

GE(rms)

channel-to-channel gain

matching (RMS value)

maximum coarse gain;

Tamb =25 °C

−

minimum coarse gain;

Tamb =25 °C

−

Clamps

PCLP

precision

black level noise on RGB

channels = 10 mV (max.)

(RMS value); Tamb =25 °C

−1

−

LSB

tCOR1

clamp correction time to within

±10 mV

±100 mV black level input

variation;

clamp capacitor = 4.7 nF

−−

300

tCOR2

clamp correction time to less

than 1 LSB

±100 mV black level input

variation;

clamp capacitor = 4.7 nF

−−

lines

tW(CLP)

clamp pulse width

500

−

2000

CLPE

channel-to-channel clamp

matching

−1

−

LSB

Aoff

code clamp reference

clamp register input

code = 0

−−63.5

−

LSB

clamp register input

code = 255

−

LSB

Phase-locked loop

jPLL(rms)

long term PLL jitter

(RMS value)

fCLK = 60 MHz; see Table 13 −

450

−

fCLK = 100 MHz;

see Table 13

−

360

−

divider ratio

100

−

4095

fref

reference clock frequency

range

−

280

kHz

fPLL

output clock frequency range

−

100

MHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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