TDA8752 datasheet(25/36 Pages) PHILIPS

25 / 36 page

1999 Mar 09

Philips Semiconductors

Product speciﬁcation

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

tCOASTmax

maximum coast mode time

−−

lines

trecap

PLL recapture time

when coast mode is aborted

−

lines

tcap

PLL capture time

in start-up conditions

−−

5ms

Φstep

phase shift step

Tamb =25 °C

−

11.25

−

deg

ADCs

maximum sampling frequency

TDA8752/6

−−

MHz

TDA8752/8

100

−−

MHz

INL

DC integral non linearity

from IC analog input to

digital output; ramp input;

fCLK = 100 MHz

−±0.5

±1.5

LSB

DNL

DC differential non linearity

from IC analog input to

digital output; ramp input;

fCLK = 100 MHz

−±0.5

±1.0

LSB

ENOB

effective number of bits

from IC analog input to

digital output; 10 kHz sine

wave input; ramp input;

fCLK = 100 MHz; note 1

−

7.4

−

bits

Signal-to-noise ratio

S/N

signal-to-noise ratio

maximum gain;

fCLK = 100 MHz

−

minimum gain;

fCLK = 100 MHz

−

Spurious free dynamic range

SFDR

spurious free dynamic range

maximum gain;

fCLK = 100 MHz

−

minimum gain;

fCLK = 100 MHz

−

Clock timing output (CKADCO, CKBO and CKAO)

ηext

ADC clock duty cycle

100 MHz output

fCLK(max)

maximum clock frequency

100

−−

MHz

Clock timing input (CKEXT)

fCLK(max)

maximum clock frequency

100

−−

MHz

tCPH

clock pulse width HIGH

3.6

−−

tCPL

clock pulse width LOW

4.5

−−

td(CLKO)

delay from CKEXT to

CKADCO

INV set to LOW

13.6

14.7

15.2

INV set to HIGH

−−

∆tsample

time difference between

samples

operating in the same supply

and temperature condition

−

0.1

0.3

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CLK

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